[English / Japanese]

Hiroki Matsutani



Assistant Professor, Dept. of Information and Computer Science, Keio University


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Youtube Video (4 Min): [Japanese] [English]
Google Scholar Citations: [Hiroki Matsutani]
Keywords: Computer Architecture, Interconnection Networks, Big Data Processing
(Last updated 2016-05-19)

Biography


Journal (International)

  1. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems", IEICE Transactions on Electronics, Special Section on Low-Power and High-Speed Chips, Vol.xx, No.xx, pp.xxx-xxx, 2016. (to appear)

  2. Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh, "Optical Network Technologies for HPC: Computer-Architects Point of View", IEICE Electronics Express, Vol.13, No.6, pp.1-14, Mar 2016.

  3. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, "Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24, No.2, pp.493-506, Feb 2016.

  4. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface", ACM SIGARCH Computer Architecture News (CAN), Vol.43, No.4, pp.22-27, Sep 2015. [Paper]

  5. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, "Swap-and-randomize: A Method for Building Low-latency HPC Interconnects", IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.26, No.7, pp.2051-2060, Jul 2015.

  6. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries", ACM SIGARCH Computer Architecture News (CAN), Vol.42, No.4, pp.75-80, Sep 2014. [Paper]

  7. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs", IPSJ Transactions on System LSI Design Methodology (T-SLDM), Vol.7, pp.27-36, Feb 2014.

  8. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "3D NoC with Inductive-Coupling Links for Building-Block SiPs", IEEE Transactions on Computers (TC), Vol.63, No.3, pp.748-763, Mar 2014.

  9. Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface", IEEE Micro, Vol.33, No.6, pp.6-15, Dec 2013.

  10. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, "Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs", IEICE Transactions on Information and Systems, Vol.E96-D, No.12, pp.2753-2764, Dec 2013.

  11. Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki, "Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems", IEEE Micro, Vol.32, No.6, pp.52-61, Dec 2012.

  12. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip", International Journal of Networking and Computing (IJNC), Vol.1, No.2, pp.244-259, Jul 2011.

  13. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors", IEEE Transactions on Computers (TC), Vol.60, No.6, pp.783-799, Jun 2011.

  14. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.30, No.4, pp.520-533. Apr 2011.

  15. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Semi-deflection Routing: A Non-minimal Fully-adaptive Routing for Virtual Cut-through Switching Network", International Journal of Computer and Network Security (IJCNS), Vol.2, No.10, pp.52-58, Oct 2010.

  16. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano, "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.20, No.8, pp.1126-1141, Aug 2009. (IEEE Computer Society Japan Chapter Young Author Award)

  17. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs", IEICE Transactions on Information and Systems, Vol.E92-D, No.4, pp.575-583, Apr 2009.

  18. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs", IEICE Transactions on Information and Systems, Vol.E90-D, No.12, pp.1914-1922, Dec 2007.


International Conference

  1. Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi, "Randomly Optimized Grid Graph for Low-Latency Interconnection Networks", Proc. of the 45th International Conference on Parallel Processing (ICPP'16), pp.xxx-xxx, Aug 2016. (to appear)

  2. Korechika Tamura, Hiroki Matsutani, "An In-Kernel NOSQL Cache for Range Queries Using FPGA NIC", Proc. of the 1st International Conference on FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC'16), May 2016. [Paper]

  3. Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "D-TDMA Data Buses with CSMA/CD Arbitration Bus on Wireless 3D IC", Proc. of the 13th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'16), pp.242-249, Feb 2016.

  4. Daichi Fujiki, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Randomizing Packet Memory Networks for Low-latency Processor-memory Communication", Proc. of the 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'16), pp.168-175, Feb 2016.

  5. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, "On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck", Proc. of the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'15), pp.16:1-16:8, Sep 2015.

  6. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips", Proc. of the 9th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'15), pp.41-48, Sep 2015.

  7. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, "3D Shared Bus Architecture Using Inductive Coupling Interconnect", Proc. of the 9th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'15), pp.259-266, Sep 2015.

  8. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Document-Oriented Databases using GPU and Cache Structure", Proc. of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'15), pp.108-115, Aug 2015. [Paper]

  9. Seiichi Tade, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Metamorphotic Network-on-Chip for Various Types of Parallel Applications", Proc. of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'15), pp.98-105, Jul 2015.

  10. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface", Proc. of the 6th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'15), Jun 2015. (Best Paper Award)

  11. Shin Morishima, Hiroki Matsutani, "A GPU-Based Acceleration Method for Document-Oriented Databases", The 6th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'15), Poster session, Jun 2015.

  12. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, "3D Bus Architecture using Inductive Coupling ThruChip-Interface", The Poster Session at the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr 2015.

  13. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Staggered Stacking: Connecting Many Small Chips Using ThruChip Interface", The Poster Session at the 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr 2015.

  14. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Optimized Core-links for Low-latency NoCs", Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'15), pp.172-176, Mar 2015.

  15. Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova, "Augmenting Low-latency HPC Network with Free-space Optical Links", Proc. of the 21st IEEE International Symposium on High-Performance Computer Architecture (HPCA'15), pp.390-401, Feb 2015. [Paper] [Slide]

  16. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries", The 5th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'14), Jun 2014.

  17. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, "Skywalk: a Topology for HPC Networks with Low-delay Switches", Proc. of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS'14), pp.263-272, May 2014.

  18. Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "On/Off Link Selection Schemes for Wireless 3D NoCs", The Poster Session at the 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Apr 2014.

  19. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", The Poster Session at the 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Apr 2014. (Featured Poster Award)

  20. Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano, "Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips", Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE'14), pp.1-6, Mar 2014. [Paper] [Slide]

  21. Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity", Proc. of the International Symposium on Advances of Distributed and Parallel Computing (ADPC'13), pp.77-85, Dec 2013.

  22. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, "Performance Degradation by Deactivated Cores in 2-D Mesh NoCs", Proc. of the 7th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'13), pp.25-30, Sep 2013.

  23. Yusuke Kumura, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "A Low-Power Link Speed Control Method on Distributed Real-time Systems", Proc. of the 7th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'13), pp.49-54, Sep 2013.

  24. Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usam, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface", The Poster Session at the 25th IEEE Symposium on High Performance Chips (Hot Chips 25), Poster session, Aug 2013.

  25. Daisuke Sasaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Deadlock-Free Routing Strategy for Stacking 3-D NoCs with Different Topologies", Proc. of the 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'13), Poster session, Jun 2013.

  26. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano "Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture", Proc. of the 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'13), pp.29-36, Apr 2013. [Paper]

  27. Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface", Proc. of the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), pp.1-3, Apr 2013.

  28. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive-Coupling Links", Proc. of the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), pp.1-3, Apr 2013.

  29. Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "Performance and Energy Optimization of a Heterogeneous Multi-Core Processor with Inductive Coupling Links", The Poster Session at the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Poster session, Apr 2013. (Best Poster Award)

  30. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Low Latency Network Topology Using Multiple Links at Each Host", The Poster Session at the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Poster session, Apr 2013.

  31. Osamu Yoshizumi, Hiroki Matsutani, Nobuyuki Yamasaki, "Packet Routing for Distributed Real-Time System on Real-Time Communication Link", Proc. of the 28th ISCA International Conference on Computers and Their Applications (CATA'13), pp.197-204, Mar 2013.

  32. Kazutoshi Suito, Masayoshi Takasu, Rikuhei Ueda, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki, "Experimental Evaluation of Low Power Techniques on Dependable Responsive Multithreaded Processor", Proc. of the 28th ISCA International Conference on Computers and Their Applications (CATA'13), pp.281-288, Mar 2013.

  33. Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova, "Layout-conscious Random Topologies for HPC Off-chip Interconnects", Proc. of the 19th IEEE International Symposium on High-Performance Computer Architecture (HPCA'13), pp.484-495, Feb 2013. [Paper] [Slide]

  34. Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "A Case for Wireless 3D NoCs for CMPs", Proc. of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), pp.23-28, Jan 2013. (Best Paper Award) [Paper] [Slide]

  35. Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, NoriyukiMiura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "Dynamic Power Control with a Heterogeneous Multi-Core System Using A 3-D Wireless Inductive Coupling Interconnect", Proc. of the 11th IEEE International Conference on Field Programmable Technology (ICFPT'12), Demo session, pp.293-296, Dec 2012.

  36. Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router", Proc. of the 6th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'12), pp.59-66, Sep 2012.

  37. Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "CMA-Cube: A Scalable Reconfigurable Accelerator with 3-D Wireless Inductive Coupling Interconnect", Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL'12), Poster session, pp.543-546, Aug 2012.

  38. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova, "A Case for Random Shortcut Topologies for HPC Interconnects", Proc. of the 39th ACM/IEEE International Symposium on Computer Architecture (ISCA'12), pp.177-188, Jun 2012. [Paper] [Slide]

  39. Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki, "Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems", Proc. of the 15th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XV), pp.1-3, Apr 2012.

  40. Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "An Extension of Real-Time OS for Multithreaded Processors", Proc. of the 18th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'12), Work-In-Progress session, Apr 2012.

  41. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, "Vertical Link On/Off Control Methods for Wireless 3-D NoCs", Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS'12), pp.212-224, Feb 2012.

  42. Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs", Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC'12), pp.407-412, Jan 2012. (Best Paper Candidate) [Paper] [Slide]

  43. Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, "Performance Evaluation of Power-aware Multi-tree Ethernet for HPC Interconnects", Proc. of the 2nd International Conference on Networking and Computing (ICNC'11), pp.50-57, Nov 2011. (Best Paper Award) [Paper] [Slide]

  44. Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor", Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), pp.9-15, Aug 2011.

  45. Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Implementation of On-chip Adaptive Router with Predictor for Regional Congestion", Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), pp.22-27, Aug 2011.

  46. Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano, "A Dynamic Link-Width Optimization for Network-on-Chip", Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), Poster session, pp.106-108, Aug 2011.

  47. Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs", Proc. of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11), pp.49-56, May 2011. [Paper] [Slide]

  48. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Variable-pipeline On-chip Router Optimized to Traffic Pattern", Proc. of the 3rd International Workshop on Network on Chip Architectures (NoCArc'10), pp.57-62, Dec 2010.

  49. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutumo Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip", Proc. of the 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS'10), pp.156-161, Nov 2010.

  50. Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks", Proc. of the 5th IEEE International Conference on Networking, Architecture, and Storage (NAS'10), pp.218-227, Jul 2010. [Paper] [Slide]

  51. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "A Deadlock-free Non-minimal Fully Adaptive Routing using Virtual Cut-through Switching", Proc. of the 5th IEEE International Conference on Networking, Architecture, and Storage (NAS'10), pp.431-438, Jul 2010.

  52. Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Yusuke Umahashi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "A Multi-Vdd Variable-Pipeline On-Chip Router for CMPs", The Poster Session at the 24th ACM International Conference on Supercomputing (ICS'10), Poster session, Jun 2010.

  53. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs", Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), pp.61-68, May 2010. [Paper] [Slide]

  54. Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Low-Power Fault-Tolerant NoC using Error Correction and Detection Codes", Proc. of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'10), pp.111-118, Feb 2010.

  55. Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Performance, Cost, and Power Evaluations of On-Chip Network Topologies in FPGAs", Proc. of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'10), pp.181-189, Feb 2010.

  56. Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Balanced Dimension-Order Routing for k-ary n-cubes", Proc. of the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'09), CD-ROM, Sep 2009.

  57. Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano, "MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link", Proc. of the 19th International Conference on Field Programmable Logic and Applications (FPL'09), pp.6-11, Sep 2009.

  58. Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, "An On/Off Link Activation Method for Power Regulation in InfiniBand", Proc. of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'09), pp.289-295, Jun 2009.

  59. Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano, "An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters", Proc. of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS'09), CD-ROM, May 2009. [Paper] [Slide]

  60. Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano, "Evaluation of a Multi-core Reconfigurable Architecture with Variable Core Size", Proc. of the 16th Reconfigurable Architectures Workshop (RAW'09), CD-ROM, May 2009.

  61. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Low-Power Variable-Pipeline Router using Pipeline-Stage Integration", Proc. of the 12th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips XII), Poster session, p.155, Apr 2009.

  62. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "Prediction Router: Yet Another Low Latency On-Chip Router Architecture", Proc. of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA'09), pp.367-378, Feb 2009. [Paper] [Slide]

  63. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems", Proc. of the 18th International Conference on Field Programmable Logic and Applications (FPL'08), pp.269-274, Sep 2008.

  64. Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano, "Three-Dimensional Layout of On-Chip Tree-Based Networks", Proc. of the 9th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'08), pp.281-288, May 2008. [Paper] [Slide]

  65. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks", Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08), pp.23-32, Apr 2008. [Paper] [Slide]

  66. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston, "A Lightweight Fault-tolerant Mechanism for Network-on-chip", Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08), pp.13-22, Apr 2008. [Paper] [Slide]

  67. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing", Proc. of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC'08), pp.55-60, Jan 2008. [Paper] [Slide]

  68. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Tightly-Coupled Multi-Layer Topologies for 3-D NoCs", Proc. of the 36th International Conference on Parallel Processing (ICPP'07), CD-ROM, Sep 2007. [Paper] [Slide]

  69. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems", Proc. of the 17th International Conference on Field Programmable Logic and Applications (FPL'07), pp.383-388, Aug 2007.

  70. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "XNoTs: Crossbar-Connected Multi-Layer Topologies for 3-D NoCs", Proc. of the 10th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips X), Poster session, pp.136, Apr 2007. [Poster]

  71. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", Proc. of the 21st IEEE International Parallel and Distributed Processing Symposium (IPDPS'07), CD-ROM, Mar 2007. [Paper] [Slide]

  72. Hiroki Matsutani, "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", The Student Forum at the 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), Poster session, Jan 2007. (Young Student Award) [Poster]

  73. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Enforcing Dimension-Order Routing in On-Chip Torus Networks without Virtual Channels", Proc. of the 4th International Symposium on Parallel and Distributed Processing and Applications (ISPA'06), pp.207-218, Dec 2006. [Paper]

  74. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks", Proc. of the 19th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS'06), pp.24-31, Sep 2006. [Paper]

  75. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano, "A Parametric Study of Scalable Interconnects on FPGAs", Proc. of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'06), pp.130-135, Jun 2006.

  76. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Kenichiro Anjo, Toru Awashima, Hideharu Amano, "An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor", Proc. of the 4th IEEE International Conference on Field Programmable Technology (ICFPT'05), pp.163-170, Dec 2005.

  77. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips", Proc. of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'05), pp.1343-1349, Jun 2005. [Paper]

  78. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano, "Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips", Proc. of the 34th International Conference on Parallel Processing Workshop / the 2nd International Workshop on Embedded Computing (ICPP-EC'05), pp.273-280, Jun 2005. [Paper] [Slide]

  79. Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai, "Mobile Gateways for Mobile Ad-hoc Networks with Network Mobility Support", Proc. of the 4th International Conference on Networking (ICN'05), pp.361-368, Apr 2005.

  80. Hiroki Matsutani, Ryuji Wakikawa, Koshiro Mitsuya, Jun Murai, "Performance Oriented Management System for Reconfigurable Network Appliances", Proc. of the 1st International Workshop on Networked Sensing Systems (INSS'04), pp.129-133, Jun 2004. [Paper]

  81. Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai, "Mobile Gateway: Integration of MANET and NEMO", The Poster Session at the 5th ACM International Symposium on Mobile Ad Hoc Networking and Computing (MobiHoc'04), Poster session, May 2004.


Journal (Japanese Domestic)

  1. Yuta Tokusashi, Hiroki Matsutani, "Design of Key-Value Store Appriance Having a Variety of Data Strcture", IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Vol.57, No.8, pp.xxx-xxx, Aug 2016. (to appear)

  2. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "A Nonparametric Online Outlier Detector for FPGA NICs", IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Vol.57, No.8, pp.xxx-xxx, Aug 2016. (to appear)

  3. Shin Morishima, Hiroki Matsutani, "GPU-Based Acceleration of Graph Search on Partitioned Graph Databases", IEICE Transactions on Information and Systems, Vol.J98-D, No.12, pp.1436-1450, Dec 2015.

  4. Tomoya Ozaki, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "A Low-Power Network Design Strategy using Free-Space Optics and On/Off Links", IEICE Transactions on Information and Systems, Vol.J98-D, No.6, pp.1005-1018, Jun 2015.

  5. Keigo Mizotani, Rikuhei Ueda, Masayoshi Takasu, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Experimental Evaluation of Temperature-Aware DVFS on Imprecise Computation Model", IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Vol.55, No.8, pp.1841-1855, Aug 2014.

  6. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "The Study of Low-latency On-chip Topology using Multiple Core Links", IEICE Transactions on Information and Systems, Vol.J97-D, No.3, pp.601-613, Mar 2014.

  7. Taniguchi Masakazu, Yamazaki Daiki, Sasagawa Yujiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Router Microarchitectures for Reducing Priority Inversions in Priority-Aware On-Chip-Networks", IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Vol.54, No.7, pp.1861-1872, Jul 2013.

  8. Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Implementation of ITRON Specification OS for RMT Processor", IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Vol.54, No.7, pp.1835-1848, Jul 2013.

  9. Kazutoshi Suito, Takuma Kogo, Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki, "Prioritized On-Chip Router VIX", IPSJ Transactions on Advanced Computing Systems, Vol.6, No.1, pp.87-98, Jan 2013.

  10. Kazutoshi Suito, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Implementation of Dependable Communication Mechanism on Responsive Link for Distributed Real-Time Systems", IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Vol.53, No.12, pp.2728-2739, Dec 2012.

  11. Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki, "A Prediction-Based Congestion Avoidance Scheme for NoCs", IPSJ Transactions on Advanced Computing Systems, Vol.5, No.3, pp.112-123, May 2012.

  12. Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura, "Adaptive Data Compression on 3D Network-on-Chips", IPSJ Transactions on Advanced Computing Systems, Vol.5, No.1, pp.80-87, Jan 2012.

  13. Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Low Power Network-on-Chip Using Error Detection and Correction Codes", IPSJ Transactions on Advanced Computing Systems, Vol.4, No.4, pp.24-35, Oct 2011.

  14. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "Evaluations of Fine-Grained Power-Gating of On-Chip Router for CMPs", IPSJ Transactions on Advanced Computing Systems, Vol.3, No.3, pp.100-112, Sep 2010.

  15. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "A Non-minimal Fully Adaptive Routing Using Single-Flit Single-Cycle Routers for NoCs", IPSJ Transactions on Advanced Computing Systems, Vol.3, No.3, pp.88-99, Sep 2010.

  16. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga "Evalutions of Prediction Router for Low-Latency On-Chip Networks", IPSJ Transactions on Advanced Computing Systems, Vol.2, No.3, pp.26-38, Sep 2009.

  17. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Study of A Variable-Pipeline Router for Network-on-Chips", IPSJ Transactions on Advanced Computing Systems, Vol.2, No.3, pp.71-82, Sep 2009.

  18. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "An Adaptive Activation Scheme for On-chip Tree-based Networks", IPSJ Transactions on Advanced Computing Systems, Vol.1, No.2, pp.70-82, Aug 2008.

  19. Michihiro Koibuchi, Tsutomu Yoshinaga, Hirokazu Murakami, Hiroki Matsutani, Hideharu Amano, "A Low-Latency Network-on-Chip using Predictive Routers", IPSJ Transactions on Advanced Computing Systems, Vol.1, No.2, pp.59-69, Aug 2008.

  20. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "The Study of Fat H-Tree Topology for Network-on-Chips", IPSJ Transactions on Advanced Computing Systems, Vol.48, No.SIG 13 (ACS19), pp.178-191, Aug 2007. (IPSJ Best Paper Award)

  21. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Virtual-Channel Free Routing Strategy for On-Chip Torus Networks", IPSJ Transactions on Advanced Computing Systems, Vol.47, No.SIG 12 (ACS15), pp.12-24, Sep 2006.

  22. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Kenichiro Anjo, Toru Awashima, Hideharu Amano, "An Adaptive Cryptographic Accelerator for IPsec on the Dynamically Reconfigurable Processor", IEICE Transactions on Information and Systems, Vol.J89-D, No.4, pp.743-754, Apr 2006.

  23. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano, "Non-Minimal Routing Strategy for Networks-on-Chips", IPSJ Transactions on Advanced Computing Systems, Vol.46, No.SIG 12 (ACS11), pp.73-83, Aug 2005.

  24. Hiroki Matsutani, Ryuji Wakikawa, Keisuke Uehara, Jun Murai, "Mobile IPv6 Profile for Embedded Systems", IPSJ Journal, Vol.45, No.10, pp.2314-2323, Oct 2004. [Paper]


Japanese Domestic Conference/Meeting

  1. Hiroaki Komatsu, Hiroki Matsutani, "A Dynamic Memory Selection Strategy for Key-Value Store Appliances with DRAMs and SSDs", IEICE Technical Reports RECONF2016-xxx, Vol.xxx, No.xxx, pp.xx-xx, May 2016. (to appear)

  2. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "An Effective Virtual Channel Allocation Method for Deterministic Deadlock-free Routing", IEICE Technical Reports CPSY2015-148 (ETNET'16), Vol.115, No.518, pp.163-168, Mar 2016.

  3. Hideharu Amano, Kimiyoshi Usami, Tadahiro Kuroda, Masaaki Kondo, Yasuhiro Take, Hiroshi Nakamura, Mitaro Namiki, Hiroki Matsutani, "An Implementation of A Building Block System with TCI (Thru-Chip Interface) Using SOTB Process", IEICE Technical Reports ICD2015-105, Vol.115, No.477, pp.49-54, Mar 2016.

  4. Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani, "Performance Evaluations on Reduction and Transformation of Spark Using GPU", IEICE Technical Reports CPSY2015-113, Vol.115, No.399, pp.25-30, Jan 2016.

  5. Korechika Tamura, Hiroki Matsutani, "Performance Improvement on In-Kernel NOSQL Cache for Range Queries", IEICE Technical Reports CPSY2015-117, Vol.115, No.399, pp.73-78, Jan 2016.

  6. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, "An Efficient NoC with Decentralized Routers", IEICE Technical Reports CPSY2015-127, Vol.115, No.399, pp.149-154, Jan 2016.

  7. Hiroaki Hara, Tomoya Ozaki, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "Latency Reduction on Inter-Component Communication across Racks using FSO", IEICE Technical Reports CPSY2015-129, Vol.115, No.399, pp.161-166, Jan 2016.

  8. Kohei Nakamura, Ami Hayashi, Hiroki Matsutani, "A Low-Latency Batch Processing for Stream Data Using FPGA NIC", IEICE Technical Reports RECONF2015-62, Vol.115, No.400, pp.19-24, Jan 2016.

  9. Hiroshi Nakahara, Daichi Fujiki, Seiichi Tade, Ryota Yasudo, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Koji Nakano, Hideharu Amano, "Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint", IEICE Technical Reports CPSY2015-104, Vol.115, No.374, pp.111-116, Dec 2015.

  10. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "A Low Latency Distributed Routing Method for Random Topologies in HPC Networks", IEICE Technical Reports CPSY2015-103, Vol.115, No.374, pp.105-110, Dec 2015. (IEICE ICD Young Presentation Award)

  11. Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "CSMA/CD and D-TDMA Hybrid Wireless 3D Bus Architecture", IEICE Technical Reports CPSY2015-69 (DesignGaia'15), Vol.115, No.342, pp.45-50, Dec 2015.

  12. Akio Nomura, Hiroki Matsutani, Yasuhiro Take, Mitaro Namiki, Tadahiro Kuroda, Hideharu Amano, "A Preliminary Evaluation of Linear Network Using ThruChip Interface", IEICE Technical Reports CPSY2015-68 (DesignGaia'15), Vol.115, No.342, pp.39-44, Dec 2015.

  13. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Document-Oriented Databases using Remote GPU Cluster", IEICE Technical Reports CPSY2015-61 (DesignGaia'15), Vol.115, No.342, pp.1-6, Dec 2015.

  14. Tomoya Ozaki, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "A Routing Strategy for Dynamic Link Allocation Using FSO", IEICE Technical Reports CPSY2015-44 (SWoPP'15), Vol.115, No.174, pp.281-286, Aug 2015.

  15. Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Layout Method of High-Radix Topology onto 3D Stacking Chips", IEICE Technical Reports CPSY2015-43 (SWoPP'15), Vol.115, No.174, pp.275-280, Aug 2015.

  16. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "A Nonparametric Online Outlier Detector for FPGA NICs", IEICE Technical Reports CPSY2015-42 (SWoPP'15), Vol.115, No.174, pp.269-274, Aug 2015. (IPSJ ARC Young Researcher Encouragement Award)

  17. Yuta Tokusashi, Hiroki Matsutani, "A Cache Hierarchy in Kernel and NIC for NOSQL Acceleration", IEICE Technical Reports CPSY2015-34 (SWoPP'15), Vol.115, No.174, pp.185-190, Aug 2015.

  18. Seiichi Tade, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Topology Alterable NoC with Fault Tolerance", IEICE Technical Reports CPSY2015-28 (SWoPP'15), Vol.115, No.174, pp.143-148, Aug 2015.

  19. Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Random Memory Network Design for Hybrid Memory Cubes", IEICE Technical Reports CPSY2015-21 (SWoPP'15), Vol.115, No.174, pp.65-70, Aug 2015.

  20. Naoaki Kashiwagi, Hiroki Matsutani, "An IP-NoC Translator for Connecting NoCs and Internet", IEICE Technical Reports CPSY2015-6, Vol.115, No.7, pp.31-36, Apr 2015.

  21. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, "3D Shared Bus Architecture Using Inductive-Coupling Interconnect", IEICE Technical Reports CPSY2015-4, Vol.115, No.7, pp.19-24, Apr 2015.

  22. Yuta Tokusashi, Hiroki Matsutani, "A Case for Accelerating Data Structure Sever using FPGA NIC", IEICE Technical Reports CPSY2014-162 (ETNET'15), Vol.114, No.506, pp.1-6, Mar 2015. (IEICE CPSY Young Presentation Award)

  23. Shin Morishima, Hiroki Matsutani, "Performance Acceleration of Document-Oriented Stores Using GPUs", IEICE Technical Reports CPSY2014-122, Vol.114, No.427, pp.1-6, Jan 2015.

  24. Korechika Tamura, Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "Accelerating NOSQLs using FPGA NIC and In-Kernel Key-Value Cache", IEICE Technical Reports CPSY2014-123, Vol.114, No.427, pp.7-12, Jan 2015.

  25. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "An Online Outlier Detector for FPGA NICs", IEICE Technical Reports CPSY2014-124, Vol.114, No.427, pp.13-18, Jan 2015.

  26. Natsuki Homma, Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "Turbo Boost Router: An On-Chip Router Supporting Deterministic and Adaptive Routings", IEICE Technical Reports CPSY2014-125, Vol.114, No.427, pp.19-24, Jan 2015.

  27. Masataka Matsumura, Masaaki Kondo, Hiroki Matsutani, Yasutaka Wada, Hiroki Honda, "A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors", IEICE Technical Reports CPSY2014-161, Vol.114, No.427, pp.245-250, Jan 2015.

  28. Hiroshi Nakahara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Scalable and Low Latency Structure for Castle of Chips", IEICE Technical Reports CPSY2014-79 (DesignGaia'14), Vol.114, No.330, pp.39-44, Nov 2014. (IEICE CPSY Young Presentation Award)

  29. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, "A Distributed Router Architecture using Transparent Latches for Networks-on-Chip", IEICE Technical Reports CPSY2014-80 (DesignGaia'14), Vol.114, No.330, pp.45-50, Nov 2014.

  30. Shin Morishima, Hiroki Matsutani, "GPU-Based Acceleration on Partitioned Graph Databases", IEICE Technical Reports CPSY2014-38 (SWoPP'14), Vol.114, No.155, pp.167-172, Jul 2014. [Paper]

  31. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches", IEICE Technical Reports CPSY2014-20 (SWoPP'14), Vol.114, No.155, pp.61-66, Jul 2014.

  32. Seiichi Tade, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Alterable Uniform and Random NoC Through Rewiring", IEICE Technical Reports CPSY2014-22 (SWoPP'14), Vol.114, No.155, pp.73-78, Jul 2014.

  33. Mao Hatto, Takaaki Miyajima, Hiroki Matsutani, Hideharu Amano, "Optimized HOG for Database System", IEICE Technical Reports RECONF2014-3, Vol.114, No.75, pp.11-16, Jun 2014.

  34. Akihiko Hamada, Hiroki Matsutani, "A Hardware Cache Mechanism for Column-Oriented Databases", IEICE Technical Reports CPSY2014-5, Vol.114, No.21, pp.21-26, Apr 2014. [Paper] [Slide] (IEICE CPSY Young Presentation Award)

  35. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "HPC Interconnect for High Topological Embeddability by Supplementary Optical Circuit Switches", IEICE Technical Reports CPSY2013-111 (ETNET'14), Vol.113, No.497, pp.253-258, Mar 2014.

  36. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", IEICE Technical Reports RECONF2013-77, Vol.113, No.418, pp.125-130, Jan 2014.

  37. Shin Morishima, Hiroki Matsutani, "Performance Evaluation of Graph Database using Multicore and GPU", IEICE Technical Reports CPSY2013-92, Vol.113, No.417, pp.113-118, Jan 2014. [Paper] (IEICE CPSY Young Presentation Award)

  38. Tomoya Ozaki, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "A Case for Low-Power Networks using FSO and On/Off Links", IEICE Technical Reports CPSY2013-85, Vol.113, No.417, pp.73-78, Jan 2014.

  39. Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "A Vertical Link On/Off Algorithm for Wireless 3-D NoCs", IEICE Technical Reports CPSY2013-84, Vol.113, No.417, pp.67-72, Jan 2014.

  40. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A 3-D NoC Architecture using CSMA/CD Bus for Inter-Chip Wireless Communication", IEICE Technical Reports CPSY2013-72 (DesignGaia'13), Vol.113, No.324, pp.77-82, Nov 2013.

  41. Keigo Mizotani, Rikuhei Ueda, Masayoshi Takasu, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Temperature-Aware DVFS on Imprecise Computation Model", Embedded Systems Symposium (ESS'13), pp.17-26, Oct 2013.

  42. Hideharu Amano, Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "A Chip Evaluation of Cube-1: A Multi-Core Processor with 3D TCI", IEICE Technical Reports CPSY2013-33, Vol.113, No.234, pp.13-18, Oct 2013.

  43. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "An Extension of Routing Strategy for Wireless Bus-Based 3-D NoCs", IEICE Technical Reports CPSY2013-18 (SWoPP'13), Vol.113, No.169, pp.49-54, Aug 2013. (IEICE CPSY Young Presentation Award)

  44. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "A Low Latency Topology for NoC Using Multiple Host Links", IEICE Technical Reports CPSY2013-9, Vol.113, No.21, pp.49-54, Apr 2013. (IEICE CPSY Young Presentation Award)

  45. Hiroki Matsutani, "A Case for Query Processing Hardware for Service-Oriented Routers", IPSJ SIG Technical Reports 2013-EMB-28 (ETNET'13), No.29, Mar 2013. [Paper] [Slide]

  46. Keigo Mizotani, Rikuhei Ueda, Masayoshi Takasu, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "A Temperature-Aware DVFS Control on Imprecise Computation Model", IEICE Technical Reports CPSY2012-88 (ETNET'13), Vol.112, No.481, pp.217-222, Mar 2013.

  47. Akihiro Takahashi, Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "A Dynamic Reconfiguration Scheme of Channel Coding on Responsive Link", IEICE Technical Reports CPSY2012-91 (ETNET'13), Vol.112, No.481, pp.235-240, Mar 2013.

  48. Takumi Ishida, Daiki Yamazaki, Masakazu Taniguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Implementation of Prioritized On-chip Network with Priority Inversion Avoidance", IEICE Technical Reports CPSY2012-73, Vol.112, No.376, pp.99-104, Jan 2013.

  49. Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "Low Power Packet Transfer Technique on Distributed Real-Time Systems", IEICE Technical Reports CPSY2012-75, Vol.112, No.376, pp.111-116, Jan 2013.

  50. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Low Latency Network Topology Using Multiple Links at Each Host", IEICE Technical Reports CPSY2012-75, Vol.112, No.376, pp.123-128, Jan 2013.

  51. Michihiro Koibuchi, Ikki Fujiwara, Yohei Hasegawa, Yoichi Hashimoto, Hiroki Matsutani, Hideharu Amano, "HPC Interconnection Networks with Short-length Cabling and Variable Topology using Free Space Optical Links", IPSJ SIG Technical Reports 2012-ARC-202 (HOKKE'12), No.14, Dec 2012. (IPSJ ARC Young Researcher Encouragement Award) [Slide]

  52. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Routing Strategy for 3-D NoCs Incorporating Bus and Network", IEICE Technical Reports CPSY2012-50 (DesignGaia'12), Vol.112, No.322, pp.15-20, Nov 2012.

  53. Masayoshi Takasu, Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki,, "Experimental Evaluation of Low Power Techniques on An Embedded Processor", Embedded Systems Symposium (ESS'12), pp.79-86, Oct 2012.

  54. Hiroaki Nishi, Hiroki Matsutani, Ryogo Kubo, Shin-ichi Ishida, Toshio Shimojo, Keisuke Iwasaki, Hideyuki Kawashima, Ikki Fujiwara, Michihiro Koibuchi, Masashi Tadokoro, "The Service-oriented-Router Infrastructure", IEICE Technical Reports IN2012-76, Vol.112, No.230, pp.13-17, Oct 2012.

  55. Kawase Daiki, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "Implementation and Evaluation of Distributed TLB Mechanism for Heterogeneous Multi-Core Processors", DA Symposium 2012 (DAS'12), pp.79-84, Aug 2012.

  56. Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Fine-Grained Power Control Using A Multi-Voltage Variable Pileline Router", IPSJ SIG Technical Reports 2012-ARC-200, No.15, Apr 2012.

  57. Daisuke Sasaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Method for Routing in a Mixed Topology of 3-D NoC", IEICE Technical Reports CPSY2011-2, Vol.112, No.2, pp.7-12, Apr 2012.

  58. Osamu Yoshizumi, Hiroki Matsutani, Nobuyuki Yamasaki, "Packet Routing for Distributed Read-Time System using Responsive Link", IPSJ SIG Technical Reports 2012-EMB-24 (ETNET'12), No.24, Mar 2012.

  59. Kawase Daiki, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Implementation of Distributed TLB Mechanism for Heterogeneous Multi-Core Processors", IEICE Technical Reports CPSY2011-84 (ETNET'12), Vol.111, No.461, pp.85-90, Mar 2012.

  60. Yuki Kawaguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Implementation of I/O Control Mechanism for Heterogeneous Multi-Core Processors", IEICE Technical Reports CPSY2011-85 (ETNET'12), Vol.111, No.461, pp.91-96, Mar 2012.

  61. Yasuhito Ito, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Implementation of Embedded Java VM for Multithreaded Processor", IEICE Technical Reports CPSY2011-89 (ETNET'12), Vol.111, No.461, pp.181-186, Mar 2012.

  62. Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Extension of ITRON Specification OS for Multithreaded Processors", IEICE Technical Reports CPSY2011-61, Vol.111, No.398, pp.43-48, Jan 2012.

  63. Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router", IEICE Technical Reports CPSY2011-62, Vol.111, No.398, pp.49-54, Jan 2012.

  64. Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki, "A Bandwidth Control Scheme Based on a Traffic Analysis for an On-Chip Router", IEICE Technical Reports CPSY2011-64, Vol.111, No.398, pp.61-66, Jan 2012.

  65. Kazutoshi Suito, Osamu Yoshizumi, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Evaluation of Dependable Real-Time Communication Method Based on Responsive Link", IPSJ SIG Technical Reports 2011-ARC-197 (HOKKE'11), No.8, Nov 2011.

  66. Yujiro Sasagawa, Hiroki Matsutani, Nobuyuki Yamasaki, "A Priority-Aware On-Chip Network Router for Reducing Priority Inversions", IEICE Technical Reports CPSY2011-50 (DesignGaia'11), Vol.111, No.328, pp.41-46, Nov 2011. (IEICE CPSY Young Presentation Award)

  67. Eiichi Sasaki, Daisuke Sasaki, Hiroki Matsutani, Hideharu Amano, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, "3-D Stacked Architecture using Inductive Coupling", IEICE Technical Reports CPSY2011-10, Vol.111, No.163 (SWoPP'11), pp.7-12, Jul 2011.

  68. Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura, "Data Compression on 3D Network-on-Chips for CMP", Proc. of the 9th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'11), pp.391-398, May 2011.

  69. Daisuke Sasaki, Hiroki Matsutani, Yasuhiro Take, Yuki Ono, Yukinori Nishiyama, Tadahiro Kuroda, Hideharu Amano, "Packet Transfer Networks for 3-D Stacked Chips with Inductive Coupling", Proc. of the 9th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'11), pp.399-406, May 2011.

  70. Daisuke Sasaki, Hiroki Matsutani, Yasuhiro Take, Yuki Ono, Yukinori Nishiyama, Tadahiro Kuroda, Hideharu Amano, "Proposal for A 3-D Stacked Chip and Transfer Technology by Inductive Coupling", IPSJ SIG Technical Reports 2011-ARC-193, No.2, Jan 2011.

  71. Shuai Wang, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Design of Low Power On-Chip Router with Error-Detection Re-Transfer Scheme", IPSJ SIG Technical Reports 2011-ARC-193, No.18, Jan 2011.

  72. Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "A Multi-Vdd Variable-Pipeline Router for NoCs", IPSJ SIG Technical Reports 2010-ARC-191, No.4, Oct 2010. [Paper] [Slide]

  73. Daisuke Sasaki, Hiroki Matsutani, Yasuhiro Take, Yuki Ono, Yukinori Nishiyama, Tadahiro Kuroda, Hideharu Amano, "Proposal for A 3-D Wireless Router and Bus Structure", IEICE Technical Reports RIS, Oct 2010.

  74. Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "A Study on Communication Protocols for Wireless 3-D NoC", IPSJ SIG Technical Reports 2010-ARC-190 (SWoPP'10), No.17, Aug 2010. [Paper] [Slide]

  75. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "Evaluations of Fine-Grained Power-Gating of On-Chip Router for CMPs", Proc. of the 8th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'10), pp.11-20, May 2010. [Paper] [Slide]

  76. Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Low Power Network-on-Chip Using Error Detection and Correction Codes", Proc. of the 8th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'10), pp.3-10, May 2010. (Young Research Award)

  77. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure", IEICE Technical Reports CPSY2009-60, Vol.109, No.394, pp.53-58, Jan 2010.

  78. Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "A 3-D NoC Architecture for Field Stackable CMPs using Inductive Coupling", IPSJ SIG Technical Reports 2009-ARC-186 (HOKKE'09), No.11, Dec 2009. [Paper] [Slide]

  79. Yuya Yabe, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, "Performance Evaluation of An On/Off Link Activation Method for Multi-path Ethernet", IEICE Technical Reports CPSY2009-39, Vol.109, No.296, pp.25-30, Nov 2009.

  80. Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, "Evaluations of Run-Time Power-Gating of On-Chip Routers for CMP", IPSJ SIG Technical Reports 2009-ARC-185, No.2, Oct 2009. [Paper] [Slide]

  81. Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Error Detection and Collectionon Mechanism on Network-on-Chip", IEICE Technical Reports CPSY2009-24, Vol.109, No.168 (SWoPP'09), pp.85-90, Aug 2009.

  82. Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, "An On/Off Link Regulation for Low-Power InfiniBand", IPSJ SIG Technical Reports 2009-ARC-184 (SWoPP'09), No.22, Aug 2009.

  83. Tomoaki Tateshita, Sayaka Akioka, Tsutomu Yoshinaga, Hiroki Matsutani, Michihiro Koibuchi, "Prediction Router for Low Latency Fat Tree Network", IPSJ SIG Technical Reports 2009-ARC-184 (SWoPP'09), No.31, Aug 2009.

  84. Cisse Ahmadou Dit ADI, Sayaka Akioka, Tsutomu Yoshinaga, Hiroki Matsutani, Michihiro Koibuchi, "Prediction Switching for Photonic Network-on-Chip", IPSJ SIG Technical Reports 2009-ARC-184 (SWoPP'09), No.32, Aug 2009.

  85. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "Evalutions of Prediction Router for Low-Latency On-Chip Networks", Proc. of the 7th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'09), pp.209-218, May 2009. [Paper] [Slide]

  86. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Study of A Variable-Pipeline Router for Network-on-Chips", Proc. of the 7th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'09), pp.19-26, May 2009.

  87. Sen In, Hiroki Matsutani, Daihan Wang, Michihiro Koibuchi, Hideharu Amano, "Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs", IEICE Technical Reports RECONF2009-3, Vol.109, No.26, pp.13-18, May 2009.

  88. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Design of the On-Chip Micro Mobility Protocol Supporting Task Migration for Many-Core Chips", IPSJ SIG Technical Reports 2009-ARC-183, No.2, Apr 2009. [Paper] [Slide]

  89. Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano, "An On/Off Link Activation Method for Power Saving in Multipath Ethernet", IPSJ SIG Technical Reports 2009-ARC-182, pp.121-126, Feb 2009. [Paper] [Slide]

  90. Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano, "Evaluation of a Multicore Reconfigurable Architecture", IEICE Technical Reports RECONF2008-56, Vol.108, No.414, pp.7-12, Jan 2009.

  91. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "Evalutions of Prediction Router for Low-Latency On-Chip Networks", IPSJ SIG Technical Reports 2009-ARC-181, pp.1-6, Jan 2009. (IEICE ICD Young Presentation Award) [Paper] [Slide]

  92. Hideharu Amano, Kyundong Kim, Hiroki Matsutani, Vasutan Tunbungheng, Yoshihiro Yasuda, Masaaki Kondo, Hiroshi Nakamura, Kimiyoshi Usami, "Preliminary Evaluations of SMA: A Massive Array of Low-Power Reconfigurable Processors", IEICE Technical Reports RECONF2008-40 (DesignGaia'08), Vol.108, No.300, pp.9-14, Nov 2008.

  93. Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, "Rearrangeable NoC: A Distributed Router Architecture for Exploiting Wire Delay", IPSJ SIG Technical Reports 2008-ARC-180, pp.57-62, Oct 2008. [Paper] [Slide]

  94. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "A Look-Ahead Router Architecture for Dynamic On/Off Control of Channels", IPSJ SIG Technical Reports 2008-ARC-179 (SWoPP'08), pp.133-138, Aug 2008. [Paper] [Slide]

  95. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "An Adaptive Activation Scheme for On-chip Tree-based Networks", Proc. of the 6th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'08), pp.375-384, Jun 2008. [Paper] [Slide]

  96. Michihiro Koibuchi, Tsutomu Yoshinaga, Hirokazu Murakami, Hiroki Matsutani, Hideharu Amano, "A Low-Latency Network-on-Chip using Predictive Routers", Proc. of the 6th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'08), pp.393-401, Jun 2008. [Paper] [Slide]

  97. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs", IEICE Technical Reports RECONF2008-7, Vol.108, No.48, pp.37-42, May 2008.

  98. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "A Low-Latency On-Chip Router Architecture with Prediction Mechanism", IPSJ SIG Technical Reports 2008-ARC-178, pp.99-104, May 2008. [Paper] [Slide]

  99. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston, "A Lightweight Fault-tolerant Mechanism for Network-on-Chip", IEICE Technical Reports CPSY2007-42, Vol.107, No.398, pp.9-14, Dec 2007.

  100. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Runtime Power Gating of Virtual Channels for On-Chip Routers", IPSJ SIG Technical Reports 2007-ARC-175 (DesignGaia'07), pp.21-26, Nov 2007. [Paper] [Slide]

  101. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Runtime Power Gating of Virtual Channels for On-Chip Routers", Proc. of the 11th System LSI Workshop, Poster session, pp.231-233, Nov 2007. [Poster]

  102. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Look-Ahead Routing Based Dynamic Power Shutdown for On-Chip Routers", IPSJ SIG Technical Reports 2007-ARC-174 (SWoPP'07), pp.127-132, Aug 2007. [Paper] [Slide]

  103. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Temporal Correlation Based Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs", IPSJ SIG Technical Reports 2007-ARC-174 (SWoPP'07), pp.133-138, Aug 2007.

  104. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Crossbar-Connected Multi-Layer Topologies for 3-D Network-on-Chips", IPSJ SIG Technical Reports 2007-ARC-173, pp.109-114, Jun 2007. [Paper] [Slide]

  105. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "The Study of Fat H-Tree Topology for Network-on-Chips", Proc. of the 5th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'07), pp.201-209, May 2007. (IEEE Computer Society Japan Chapter Award) [Paper] [Slide]

  106. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Fat Tree Based Network-on-Chips for 3-D ICs", IPSJ SIG Technical Reports 2007-ARC-171, pp.75-80, Jan 2007. (IPSJ Yamashita SIG Research Award) [Paper]

  107. Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Hiroki Matsutani, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Toru Sano, Masaru Kato, Shotaro Saito, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano, "Scheduling Algorithms for Multicast Configuration", IEICE Technical Reports RECONF2006-73, Vol.106, No.458, pp.49-54, Jan 2007.

  108. Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Hiroki Matsutani, Vasutan Tunbunheng, Adepu Parimala, Takashi Nishimura, Masaru Kato, Shotaro Saito, Toru Sano, Naomi Seki, Keiichiro Hirai, Mao KaiYi, Hideharu Amano, "Implementation of Dynamically Reconfigurable Processor MuCCRA", IEICE Technical Reports RECONF2006-72, Vol.106, No.458, pp.43-48, Jan 2007.

  109. Hideharu Amano, Yohei Hasegawa, Satoshi Tsutsumi, Takuro Nakamira, Takashi Nishimura, Vasutan Tunbunheng, Adepu Parimala, Masaru Kato, Toru Sano, Shotaro Saito, Hiroki Matsutani, "MuCCRA-1: A Dynamically Reconfigurable Processor Prototype Chip", Proc. of the 29th PARTHENON Workshop, Dec 2006.

  110. Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Hiroki Matsutani, Hideharu Amano, "Performance Evaluation of Multi-core DRP for Stream Application", IEICE Technical Reports RECONF2006-52, Vol.106, No.394, pp.37-42, Nov 2006.

  111. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano, "A Parametric Study of Packet-Switched FPGA Overlay Networks", IEICE Technical Reports RECONF2006-32, Vol.106, No.247, pp.31-36, Sep 2006.

  112. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Performance Evaluation of Fat H-Tree Topology in Networks-on-Chips", IPSJ SIG Technical Reports 2006-ARC-169 (SWoPP'06), pp.109-114, Aug 2006. [Paper] [Slide]

  113. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Virtual-Channel Free Mapping for On-Chip Torus Networks", IPSJ SIG Technical Reports 2006-ARC-168, pp.101-106, Jun 2006. [Paper] [Slide]

  114. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Virtual-Channel Free Routing Strategy for On-Chip Torus Networks", Proc. of the 4th Symposium on Advanced Computing Systems and Infrastructures (SACSIS'06), pp.377-384, May 2006. [Paper] [Slide]

  115. Yohei Hasegawa, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Reconfigurable Architectures with On-Chip Networks for Multitask Designs", IEICE Technical Reports RECONF2006-5, Vol.106, No.49, pp.25-31, May 2006.

  116. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano, "Non-Minimal Routing Strategy for Networks-on-Chips", Proc. of the 3rd Symposium on Advanced Computing Systems and Infrastructures (SACSIS'05), pp.177-184, May 2005. [Paper]

  117. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Hideharu Amano, "A Routing Strategy for Networks-on-Chips with Link Faults", IEICE Technical Reports FIIS2005-156, Mar 2005.

  118. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Kenichiro Anjo, Toru Awashima, Hideharu Amano, "Switchable Multi-Cryptographic Engines for Embedded Network Security on a Dynamically Reconfigurable Processor", IEICE Technical Reports CPSY2004-92, Vol.104, No.737, pp.13-18, Mar 2005.

  119. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano, "Non-Minimal Routing Strategy for Networks-on-Chips", IPSJ SIG Technical Reports 2005-ARC-162 (HOKKE'05), pp.169-174, Mar 2005. [Paper]

  120. Yutaka Yamada, Michihiro Koibuchi, Kenichiro Anjo, Hiroki Matsutani, Akiya Jouraku, Hideharu Amano, "Analysis about Topologies of Network on Chip", IPSJ SIG Technical Reports 2004-ARC-160 (DesignGaia'04), pp.35-40, Dec 2004.

  121. Hiroki Matsutani, Ryuji Wakikawa, Keisuke Uehara, Jun Murai, "Design of Mobile IPv6 Profile for Embedded System", Proc. of Multimedia, Distributed, Cooperative and Mobile Symposium (DICOMO'03), pp.101-104, Jun 2003. (Paper Award) [Paper]

  122. Ryuji Wakikawa, Masafumi Watari, Hiroki Matsutani, Koshiro Mitsuya, Thierry Ernst, Keisuke Uehara, Jun Murai, "Demonstration System supporting Host and Network Mobility", Proc. of Multimedia, Distributed, Cooperative and Mobile Symposium (DICOMO'03), pp.617-620, Jun 2003. [Paper]

  123. Hiroki Matsutani, Ryuji Wakikawa, Jun Murai, "Design and Implementation of Sensor Nodes for InternetCARs", Proc. of Internet Conference 2002 (IC'02), Work-in-Progress, p.121, Oct 2002. (Demonstration Award) [Paper]


Invited Talk and Tutorial

  1. Hiroki Matsutani, "Accelerator Design for Various NOSQL Databases", International Forum on MPSoC for Software-defined Hardware (MPSoC'16), Invited Talk, Jul 2016. (to appear)

  2. Hiroki Matsutani, "Inductive-Coupling 3D Wireless NoC Designs", The 29th International Conference on VLSI Design (VLSID'16), Special Session (Video Presentation), Jan 2016.

  3. Hiroki Matsutani, "A Reconfigurable Database Platform for Integrating Various Structured Storages", The 77th National Convention of IPSJ, CREST/PRESTO "Big Data" Project Accomplishment Report, Mar 2015. [Niconico Video]

  4. Hiroki Matsutani, "Accelerator Design for Various NOSQL Databases", Big Data French-Japanese Workshop, The Embassy of France in Japan, Invited Talk, Nov 2014.

  5. Hiroki Matsutani, "Research Trends and Activities on Computer Architecture for Big Data", Internet Conference 2014 (IC'14), Invited Talk, Nov 2014.

  6. Hiroki Matsutani, "Digital VLSI Design using Open Cell Library", IEICE Society Conference 2014, Tutorial, Sep 2014. [Paper]

  7. Hiroki Matsutani, "3D WiNoC Architectures", The 8th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'14), Special Session, Sep 2014. [Slide]

  8. Hiroki Matsutani, "NoSQL Accelerator Design for Polyglot Persistence", IPSJ SIG Technical Reports 2014-DBS-159, Invited Talk, Aug 2014.

  9. Hiroki Matsutani, Hideyuki Kawashima, "Forefront of Big Data Research: From the Beginning to the Cutting-Edge Research Activities", Summer United Workshops on Parallel, Distributed and Cooperative Processing (SWoPP'14), Birds-of-a-Feather, Jul 2014.

  10. Hiroki Matsutani, "Accelerator Design for Various Structured Storages (NOSQLs)", NEC Corporation, Invited Talk, Jul 2014.

  11. Hiroki Matsutani, "3D WiNoC Architectures", The 17th Design, Automation, and Test in Europe Conference (DATE'14), Tutorial, Mar 2014. [Slide]

  12. Hiroki Matsutani, "Hardware-Based Accelerators for Various Structured Storages", The 76th National Convention of IPSJ, Panel Discussion, Mar 2014. [Slide]

  13. Hiroki Matsutani, "Research Challenges on 2-D and 3-D Network-on-Chips", The 1st International Symposium on Computing and Networking (CANDAR'13), Tutorial, Dec 2013.

  14. Hiroki Matsutani, "A Case for Hardware-Based Database Technologies for Embedded Systems", IPSJ SIG Technical Reports 2013-EMB-30, Invited Talk, Sep 2013.

  15. Hiroki Matsutani, "A Wireless 3-D Network-on-Chip Architecture using Inductive-Coupling for Chip-Multiprocessors", Carnegie Mellon University, CSSI Seminar, Mar 2011.

  16. Hiroki Matsutani, "Network-on-Chip: Fundamental Technologies and Recent Trends", Fujitsu Limited, Invited Talk, May 2010.

  17. Hiroki Matsutani, "Commemorative Speech for IEEE Computer Society Japan Chapter Young Author Award 2009", IEEE Computer Society Japan Chapter, Dec 2009.

  18. Koji Inoue, Keiji Kimura, Hiroki Matsutani, "Many-Core Processors and Their Supporting Technologies", Embedded Systems Symposium (ESS'09), Tutorial, Oct 2009. [Slide]

  19. Hiroki Matsutani, "Forefront of Network-on-Chip Architecture: From the Beginning to the Cutting-Edge Trends", Fukuoka Institute of System LSI Design Industry, Invited Talk, Aug 2008. [Slide]


Book Chapter

  1. Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "Chapter 10: 3-D NoC on Inductive Wireless Interconnect", Book of "3D Integration for NoC-based SoC Architectures" edited by Abbas Sheibanyrad, Frederic Petrot, Axel Janstch, pp.225-248, Springer, Dec 2010.

  2. Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, "Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks", Book of "Low Power Networks-on-Chip" edited by Cristina Silvano, Marcello Lajolo, Gianluca Palermo, pp.21-44, Springer, Oct 2010.

  3. Michihiro Koibuchi, Hiroki Matsutani, "Chapter 3: Networks-on-Chip Protocols", Book of "Networks-on-Chips: Theory and Practice" edited by Fayez Gebali, Haytham Elmiligi, Mohamed Watheq El-Kharashi, pp.65-94, CRC Press, Mar 2009.


Award

  1. "Best Paper Award", The 6th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'15).

  2. "IEICE CPSY Young Presentation Award" (2014).

  3. "IPSJ ARC Young Researcher Encouragement Award" (2013).

  4. "Best Paper Award", The 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13).

  5. "Best Paper Award", The 2nd International Conference on Networking and Computing (ICNC'11).

  6. "FFIT Funai Research Encouragement Award" (2010).

  7. "IEEE Computer Society Japan Chapter Young Author Award" (2009).

  8. "IEICE ICD Young Presentation Award" (2009).

  9. "IPSJ Best Paper Award" (2008).

  10. "IPSJ Yamashita SIG Research Award" (2007).

  11. "IEEE Computer Society Japan Chapter Award", The Symposium on Advanced Computing Systems and Infrastructures (SACSIS'07).

  12. "Young Student Award", The Student Forum at the 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07).

  13. "Paper Award", The Multimedia, Distributed, Cooperative and Mobile Symposium (DICOMO'03).

  14. "Demonstration Award", The Internet Conference (IC'02).

Nomination

  1. "Best Paper Candidate", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC'12).

For co-authors

  1. Ryuta Kawano, "IEICE ICD Young Presentation Award" (2016).

  2. Ami Hayashi, "IPSJ ARC Young Researcher Encouragement Award" (2015).

  3. Yuta Tokusashi, "IEICE CPSY Young Presentation Award" (2015).

  4. Hiroshi Nakahara, "IEICE CPSY Young Presentation Award" (2015).

  5. Shin Morishima, "IEICE CPSY Young Presentation Award" (2014).

  6. Takahiro Kagami, "IEICE CPSY Young Presentation Award" (2014).

  7. Seiichi Tade, "Featured Poster Award", The 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII).

  8. Ryuta Kawano, "IEICE CPSY Young Presentation Award" (2013).

  9. Yusuke Koizumi, "Best Poster Award", The 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI).

  10. Kawase Daiki, "IPSJ SLDM Student Presentation Award" (2012).

  11. Yuki Kawaguchi, "IPSJ SLDM Student Presentation Award" (2012).

  12. Yujiro Sasagawa, "IEICE CPSY Young Presentation Award" (2012).

  13. Yu Kojima, "Young Research Award", The Symposium on Advanced Computing Systems and Infrastructures (SACSIS'10).


Professional Service

Journals

  1. IEICE Transactions on Information and Systems, Editorial committee (May 2012 - May 2016).

  2. IPSJ Journal of Information Processing (JIP), Editorial committee (May 2012 - May 2016).

  3. IEICE Electronics Express (ELEX), Editorial committee (May 2012 - May 2015).

  4. IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Guest editor (Dec 2014), Guest editorial committee (Dec 2015, Dec 2016).

  5. IPSJ Journal of Information Processing, Special Issue of Embedded Systems Engineering, Guest associate editors-in-chief (Aug 2014, Feb 2015), Guest editorial committee (Dec 2012, Jul 2013, Feb 2014, Aug 2015, Feb 2016, Aug 2016).

  6. IPSJ Journal of Information Processing, Special Issue of Students' and Young Researchers' Papers, Guest editorial committee (Mar 2015).

  7. IPSJ Transactions on System LSI Design Methodology (T-SLDM), Special Issue on ASP-DAC 2013, Guest editorial committee (Aug 2013).

  8. IEICE Transactions on Electronics, Special Section on Hardware and Software Technologies on Advanced Microprocessors, Guest editorial committee (Oct 2009).

Conferences

  1. International Symposium on Networks-on-Chip (NOCS), Organizing committee (Technical program chair 2016), Program committee (2015, 2016).

  2. International Workshop on Data Management on New Hardware (DaMoN), Program Committee (2016).

  3. International Forum on MPSoC for Software-defined Hardware (MPSoC), Organizing committee (Publicity chair 2016).

  4. International Symposium on Low Power Electronics and Design (ISLPED), Organizing committee (Design contest chair 2015), Technical program committee (2014, 2015, 2016).

  5. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Program committee (2014, 2015, 2016).

  6. Design, Automation, and Test in Europe Conference (DATE), Technical program committee (2012, 2013, 2014, 2015, 2016).

  7. International Symposium on Computing and Networking (CANDAR), Program committee (2016).

  8. Annual Meeting on Advanced Computing System and Infrastructure (ACSI), Program committee (2015, 2016).

  9. International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS), Technical program committee (2016).

  10. Embedded Systems Symposium (ESS), Organizing committee (Program vice chair 2016), Program committee (2009, 2010, 2011, 2012, 2013, 2014, 2015).

  11. National Convention of IPSJ, Executive committee member (2016).

  12. International Green and Sustainable Computing Conference (IGSC), Technical program committee (2015).

  13. International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC), Technical program committee (2012, 2013, 2014, 2015).

  14. International Workshop on Many-core Embedded Systems (MES), Technical program committee (2014, 2015).

  15. Asia and South Pacific Design Automation Conference (ASP-DAC), Technical program committee (2012, 2013, 2014).

  16. International Conference on Reconfigurable Computing and FPGAs (ReConFig), Program committee (2013).

  17. International Conference on Parallel and Distributed Systems (ICPADS), Program committee (2013).

  18. International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Program committee (2013).

  19. International Symposium on Embedded Multicore Systems-on-Chip (MCSoC), Organizing committee (Publicity chair 2013), Program committee (2009, 2010, 2012, 2013).

  20. Symposium on Advanced Computing Systems and Infrastructures (SACSIS), Program committee (2012, 2013).

  21. International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA), Organizing committee (2011, 2012).

  22. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Technical program committee (2009, 2010, 2012).

SIGs

  1. IEICE Technical Committee on Reconfigurable Systems (SIG-RECONF), Committee (Apr 2014 - present).

  2. IPSJ Special Interest Group on System LSI Design Methodology (SIG-SLDM), Committee (Apr 2011 - Mar 2015).

  3. IPSJ Special Interest Group on Embedded Systems (SIG-EMB), Committee (Apr 2009 - Mar 2013).


Teaching

  1. Fundamentals of Computer Systems (Spring), Faculty of Science and Technology, Keio University, 2011, 2014 - present.

  2. Algorithm II (Spring), Faculty of Science and Technology, Keio University, 2012 - present.

  3. ICS Experiment II Microprocessor (Fall), Faculty of Science and Technology, Keio University, 2011 - present.

  4. VLSI Design (Spring), Faculty of Science and Technology, Keio University, 2011 - present.

  5. Advanced Course on Distributed Systems (Fall), Graduate School of Science and Technology, Keio University, 2012 - present.

Previous Courses

  1. Programming III (Fall), Faculty of Science and Technology, Keio University, 2013.

  2. Information Processing (Summer), Correspondence Course, Keio University, 2011, 2012.