Keynote Talks

Near-Field Coupling Integration Technology [Slides]

Tadahiro Kuroda (Keio University, Japan)

Abstract: IC was invented in the process of challenge to "Tyranny of Numbers" of interconnections in a large-scale system. Modern ICs integrate many miles of wiring and billions of contacts. Moore's Law, however, will die, and we cannot rely just on integration on a chip. A revolutionary solution of the connection problem is now needed for further integration. My proposal is to replace mechanical connection using wiring, solder, and connectors by electrical one using near-field coupling. In this presentation, ThruChip Interface (TCI) based on inductive coupling for chip stacking and Transmission Line Coupler (TLC) based on electromagnetic coupling for module connection will be presented and discussed. TCI will enable energy-efficient data centric computing for big data analysis and TLC will make small sensors connected like LEGO Bricks.
Biography: Tadahiro Kuroda received the Ph.D. degree in electrical engineering from the University of Tokyo. In 1982, he joined Toshiba Corporation. In 2000, he moved to Keio University, where he has been a professor since 2002. He was a Visiting MacKay Professor at the University of California, Berkeley in 2007. His research interests include low-power CMOS design, near-field-coupling integration technology, and artificial intelligence. He has published more than 200 papers, including 37 ISSCC papers, 26 VLSI Symposia papers, 19 CICC papers and 16 A-SSCC papers. He wrote 22 books/chapters and filed more than 200 patents. He is an IEEE Fellow and an IEICE Fellow.

Identifying On-Chip Communication Requirements for IOT

Rob Aitken (ARM Inc, USA)

Abstract: Two key features of leaf-node chips for the Internet of Things (IOT) are heterogeneity and low power consumption. While there will be great diversity of such chips, a typical wireless sensor node can be expected to sleep for large periods of time, wake up and perform some measurement, then periodically gather several such measurements, perform some local data analysis and upload the results via a wireless connection. Additionally, it might be called upon to initialize, change power modes, update its firmware, or instantiate a network connection. In order to perform these tasks, these chips will contain complex subsystems with multiple processors controlling a variety of functions and internal communication needs. This talk looks at these requirements and identifies the ways in which they differ from conventional NoCs, as well as areas where existing solutions can be reused.
Biography: Rob Aitken is an R&D Fellow at Director of Technology at ARM. He leads ARM's efforts in technology roadmapping, including low power design, standard cell and memory architecture, and post-Moore devices. He has given tutorials and short courses on several subjects at conferences and universities worldwide. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has published over 70 technical papers, and holds 20 US patents. He is an IEEE Fellow and holds a Ph.D. degree from McGill University in Canada.

Embedded Tutorial

Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations

Jiang Xu (Hong Kong University of Science and Technology, Hong Kong)
Shigeru Nakamura (NEC Corp., Japan)

Abstract: The massive integration of heterogeneous processing cores into a single die or system calls for a careful design of the communication infrastructure. In order to avoid the limitations of traditional electronic-based communication infrastructure (e.g., power dissipation, latency, temperature hotspots), the photonic-based communication promises ultra-high bandwidth, low latency, and great energy efficiency to alleviate the inter-rack, intra-rack, intra-board, and intra-chip communication bottlenecks in multiprocessor systems. This tutorial reviews the latest progress on silicon-based photonics devices, discusses the PHY-level interconnect modeling, the unified inter/intra-chip optical networks, crosstalk noise, and optical thermal effects, as well as highlights a number of challenges in optical interconnection networks and calls for future research on these problems.

Advanced Program

Best Paper Award

  • Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi, "A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations"

Best Paper Award Candidates

  • PROSA: Protocol-Driven NoC Architecture
  • A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations
  • PowerMax: An Automated Methodology for Generating Peak-Power Traffic in Networks-on-Chip Submission

Poster Sessions

  • Speakers of regular sessions (regardless of long or short presentations) are required to present their excellent work at a poster session on the same day for further discussion.
  • Please bring your printed poster to the conference venue. Poster board size is 1200mm (width) x 1800mm (height).
  • Please put up your poster on the designated poster board at Conference Room 1 before the poster session. Then please remove it after the poster session.

First Day (August 31st, 2016)

Opening Address (Nougaku Hall)
Keynote 1 (Nougaku Hall)
Chair: Bill Lin (University of California, San Diego)

"Near-Field Coupling Integration Technology"
Tadahiro Kuroda (Keio University, Japan)
Regular Session 1 (Nougaku Hall)
Title: Workload Modeling and Control
Chair: Zhonghai Lu (Royal Institute of Technology)

"Safe and Dynamic Traffic Rate Control for Networks-on-Chips"
Adam Kostrzewa (Technische Universitat Braunschweig, Germany), Selma Saidi (Technische Universitat Hamburg, Germany), Sebastian Tobuschat, Rolf Ernst (Technische Universitat Braunschweig, Germany)

"Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems"
Xiaohang Wang (South China University of Technology, China), Amit Kumar Singh (University of York, UK), Bing Li (South China University of Technology, China), Yang Yang (Sun Yat-sen University, China), Terrence Mak (University of Southampton)

"Tighter Time Analysis for Real-Time Traffic in On-Chip Networks with Shared Priorities"
Meng Liu, Matthias Becker, Moris Behnam, Thomas Nolte (Malardalen University, Sweden)

"Improving NoC Performance under Spatio-Temporal Variability By Runtime Reconfiguration: A General Mathematical Framework"
Yuankun Xue, Paul Bogdan (University of Southern California, USA)
Lunch (Conference Room 1)
Special Session 1 (Nougaku Hall)
Title: Extending Networks from Chips to Flexible Substrates
Chair: Hiroki Matsutani (Keio University)

"Printed Circuits on Flexible Substrates: Opportunities and Challenges"
Tsung-Ching Huang (Hewlett Packard Labs, USA), Kwang-Ting Cheng (Hong Kong University of Science and Technology, Hong Kong), Raymond Beausoleil (Hewlett Packard Labs, USA)

"Extending Networks from Chips to Flexible and Stretchable Electronics"
Ujjwal Gupta, Umit Y. Ogras (University of Arizona, USA)

"Hybrid Large-Area Systems and their Interconnection Backbone"
Naveen Verma, L. Aygun, Y. Afsar, Y. Hu, L. Huang, T. Moy, J. Sanz-Robinson, W. Rieutort-Louis, S. Wagner, J. C. Sturm (Princeton University, USA)
Regular Session 2 (Nougaku Hall)
Title: Power-Aware Design
Chair: Vassos Soteriou (Cyprus University of Technology)

"PowerMax: An Automated Methodology for Generating Peak-Power Traffic in Networks-on-Chip"
Ioannis Seitanidis (Democritus University of Thrace, Greece), Chrysostomos Nicopoulos (University of Cyprus, Cyprus), Giorgos Dimitrakopoulos (Democritus University of Thrace, Greece)

"TooT: An Efficient and Scalable Power-Gating Method for NoC Routers"
Hossein Farrokhbakht, Mohammadkazem Taram, Behnam Khaleghi, Shaahin Hessabi (Sharif University of Technology, Iran)
Poster Session (Conference Room 1)
By speakers of Regular Sessions 1 and 2
Reception (Nara National Museum)

Second Day (September 1st, 2016)

Keynote 2 (Nougaku Hall)
Chair: Partha Pratim Pande (Washington State University)

"Identifying On-Chip Communication Requirements for IOT"
Rob Aitken (ARM Inc, USA)
Regular Session 3 (Nougaku Hall)
Title: Emerging Technology
Chair: Umit Ogras (Arizona State University)

"Populating and Exploring the Design Space of Wavelength-Routed Optical Network-on-Chip Topologies by Leveraging the Add-Drop Filtering Primitive"
Mahdi Tala, Marco Castellari, Marco Balboni, Davide Bertozzi (University of Ferrara, Italy)

"Sharing a Global On-Chip Transmission Line Medium without Centralized Scheduling"
Yashar Asgarieh, Bill Lin (University of California San Diego, USA)

(*) "Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers"
Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha (Colorado State University, USA)

(*) "Design of High Bandiwdth Photonic Network-on-Chip Architectures Using Optical Multilevel Signaling"
Tzyy-Juin Kao (University of Arizona, USA), Ahmed Louri (George Washington University, USA)
Lunch (Conference Room 1)
Special Session 2 (Nougaku Hall)
Title: Silicon Photonics for On- and Off-Chip Networks and the Post-Moore Computing
Chair: Jiang Xu (Hong Kong University of Science and Technology)

"Toward Exa-scale Photonic Switch System for the Future Datacenter"
Kiyo Ishii, Shu Namiki (National Institute of Advanced Industrial Science and Technology, Japan)

"Chip-scale Si-photonics optical transceiver for a photonics - electronics convergence system"
Kazuhiko Kurata, Ichiro Ogura, Kenichiro Yashiki, Yasuyuki Suzuki Mituru Kurihara, Yasuhiko Hagihara, Takahiro Nakamura (Photonics-electronics Technology Research Association, Japan)

"Flow-centric Computing Leveraged by Photonic Circuit Switching for the Post-Moore Era"
Ryousei Takano (National Institute of Advanced Industrial Science and Technology, Japan), Tomohiro Kudoh (University of Tokyo, Japan)
Embedded Tutorial (Nougaku Hall)
Chair: Sudeep Pasricha (Colorado State University)

"Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations"
Jiang Xu (Hong Kong University of Science and Technology, Hong Kong), Shigeru Nakamura (NEC Corp., Japan)
Poster Session (Conference Room 1)
By speakers of Regular Session 3
Banquet (Reception Hall)
(*) Short presentation (15min including Q and A)

Third Day (September 2nd, 2016)

Special Session 3 (Nougaku Hall)
Title: Small-Diameter Graphs for Low-Latency NoCs
Chair: Ikki Fujiwara (National Institute of Informatics)

"A Heuristic Method of Generating Diameter 3 Graphs for Order/Degree Problem"
Teruaki Kitasuka, Masahiro Iida (Kumamoto University, Japan)

"Average Shortest Path Length of Graphs of Diameter 3"
Nobutaka Shimizu (University of Tokyo, Japan), Ryuhei Mori (Tokyo Institute of Technology, Japan)

"Constructing Large-scale Low-latency Network from Small Optimal Networks"
Ryosuke Mizuno, Yawara Ishida (Kyoto University, Japan)
Regular Session 4 (Nougaku Hall)
Title: Fault Tolerance and Asynchronous Design
Chair: Jens Sparsø (Technical University of Denmark)

"Multi-bit Transient Fault Control for NoC Links Using 2D Fault Coding Method"
Xiaowen Chen, Zhonghai Lu (Royal Institute of Technology, Sweden), Yuanwu Lei, Yaohua Wang, Shenggang Chen (National University of Defense Technology, China)

"A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations"
Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi (University of Ferrara, Italy)

"The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs"
Masashi Imai (Hirosaki University, Japan), Thiem Van Chu, Kenji Kise (Tokyo Institute of Technology, Japan), Tomohiro Yoneda (National Institute of Informatics, Japan)
Lunch (Conference Room 1)
Regular Session 5 (Nougaku Hall)
Title: Interconnection Architecture
Chair: Axel Jantsch (Vienna University of Technology)

"PROSA: Protocol-Driven NoC Architecture"
Miguel Gorgues Alonso, Jose Flich (Universitat Politecnica de Valencia, Spain)

"Using Benes Networks at Fault Tolerant and Deflection Routing based NoCs"
Armin Runge, Reiner Kolla (University of Wurzburg, Germany)

"Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips"
Behrad Niazmand, Siavoosh Payandeh Azad (Tallinn University of Technology, Estonia), Jose Flich (Universitat Politecnica de Valencia, Spain), Thomas Hollstein, Jaan Raik, Gert Jervan (Tallinn University of Technology, Estonia)

(*) "An Area-Efficient TDM NOC Supporting Reconfiguration for Mode Changes"
Rasmus Bo Sorensen, Luca Pezzarossa, Jens Sparso (Technical University of Denmark, Denmark)
Closing Remark (Nougaku Hall)
Poster Session (Conference Room 1)
By speakers of Regular Sessions 4 and 5
(*) Short presentation (15min including Q and A)

Demo and Exhibition

Demos take place at Conference Room 1 during Poster Sessions.

  • "Manycore Visualization with VR", Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Tran Thi Hong, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
  • "Network in Package for a Building Block System with Wireless Inductive Coupling Thru-Chip Interface", Hideharu Amano, Hiroki Matsutani, Tadahiro Kuroda (Keio University, Japan), Mitaro Namiki (Tokyo University of Agriculture and Technology, Japan), Kimiyoshi Usami (Shibaura Institute of Technology, Japan), Masaaki Kondo, Hiroshi Nakamura (University of Tokyo, Japan)