Advanced VLSI Design Exercises

Lecturer: Hiroki Matsutani (Dept of ICS, Matsutani Lab)
If you have any questions please contact me via Email or Slack at 1_matsutani.hiroki.

Important Notice

  • (2024-04-11) SSH/VNC setup manual is available here.
  • This is a tentative schedule which will be updated later.

    • 2024 Spring

  • Day 01 (Apr 11, 2024): Introduction [Slide]
  • Day 02 (Apr 18, 2024): Standard cell based design [Slide]
  • Day 03 (Apr 25, 2024): Verilog HDL: Basics [Slide]
  • Day 04 (May 02, 2024): Verilog HDL: Exercises [Slide]
  • Day 05 (May 09, 2024): Processor architecture [Slide]
  • Day 06 (May 16, 2024): Memory map and I/O devices [Slide]
  • Day 07 (May 23, 2024): Bus and DMA controller [Slide]
  • Day 08 (May 30, 2024): [NO CLASS]
  • Day 09 (Jun 06, 2024): Logic synthesis [Slide]
  • Day 10 (Jun 13, 2024): Placement and routing [Slide]
  • Day 11 (Jun 20, 2024): Delay and power analysis [Slide]
  • Day 12 (Jun 27, 2024): Hierarchical design [Slide]
  • Day 13 (Jul 04, 2024): Chip assembly [Slide]
  • Day 14 (Jul 11, 2024): Final report