Best Paper Award
- BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems
Amirhossein Mirhosseini (University of Michigan), Mohammad Sadrosadati, Behnaz Soltani, Hamid Sarbazi-Azad (Sharif University of Technology) and Thomas Wenisch (University of Michigan)
Panel Discussion
Title
Networks-on-Chip: Past, Present and Future
Moderators
Umit Ogras (Arizona State University) and Zhonghai Lu (KTH Royal Institute of Technology)
Panelists
- Luca Carloni (Columbia University, USA)
- Nanni de Micheli (EPFL, Switzerland) Slides
- Ahmed Hemani (KTH Royal Institute of Technology, Sweden) Slides
- Vijaykrishnan Narayanan (Pennsylvania State University, USA)
- Partha Pande (Washington State University, USA)
- Axel Jantsch (TU Wien) Slides
Abstract
Networks-on-chip have emerged as the de-facto communication paradigm for on-chip parallel distributed computing. However, overcoming the critical challenges we faced in scaling up the computational power and addressing the limitations imposed by Moore and Denard laws are not easy. For the last 15 years, we witnessed a tremendous revolution in the mathematical models, algorithms and design methodologies developed for NoC-based multicore platforms. Consequently, instead of integrating a few cores we now aim to interconnect hundreds to thousands of processing elements through an NoC environment. Entering the Internet-of-things revolution calls for for restructuring the knowledge learned, discovering and developing more scalable design methodologies to tackle the new challenges of dealing with big data and embedding intelligence within future smart infrastructure.
In this anniversary NOCS special session, pioneers, top thinkers and original scientists will review the success stories of NoC design, will discuss the main challenges that lie ahead of us, and provide inspiring visions for how NoC-based multicores can revolutionize all aspects of life from efficient highly accurate healthcare architectures to intelligent energy systems, from smart infrastructure and transportation to smart cities. This unique event is meant to stimulate a burst of creativity from the NOCS community to embark and solve the critical challenges our society faces.
Presentation Guidline
- All accepted papers shall prepare an oral presentation in 30 minutes: 25 minutes for the talk and 5 minutes for Q & A.
- There is no template for oral presentations and authors are free to choose a proper template by themselves.
- In the break before the start of their session, the presenters of papers shall give his or her short bio to the session chair for timely introduction.
- This year we have no poster presentation (only oral presentation).
Advance Program
| Thursday October 19, 2017 | ||
| Time | ||
| Breakfast | ||
Opening Ceremony
Session chairs: Umit Ogras (Arizona State University) and Zhonghai Lu (KTH Royal Institute of Technology) |
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Keynote
Session chair: Umit Ogras (Arizona State University) Networks Off Chip: High Performance Fabrics in Support of the Data Center Computer Robert Zak (Intel Corporation) |
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| Coffee Break | ||
Session 1: Efficient Router and NoC Architecture
Session chair: Hiroki Matsutani (Keio University) 17- Minimally Buffered Deflection Routing with In-Order Delivery in a Torus Jörg Mische, Christian Mellwig, Alexander Stegmeier, Martin Frieb and Theo Ungerer (University of Augsburg) 34- Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect Charles Effiong, Gilles Sassatelli and Abdoulaye Gamatie (LIRMM) 4- A Novel Approach to Reduce Packet Latency Increase caused by Power Gating in Network-on-Chip Peng Wang, Sobhan Niknam (Leiden University), Zhiying Wang (National University of Defense Technology) and Todor Stefanov (Leiden University) 29- Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling Ishan Thakkar, Sai Vineel Reddy Chittamuru and Sudeep Pasricha (Colorado State University) |
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| Lunch | ||
Session 2: Interconnect Architecture and Heterogeneous System (Best paper candidates session)
Session chair: Axel Jantsch (TU Wien) *43- Energy and Area Efficient Near Field Inductive Coupling: A Case study on 3D NoC Srinivasan Gopal, Sourav Das, Partha Pande and Deukhyoun Heo (Washington State University) *50- Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer Kshitij Bhardwaj, Weiwei Jiang and Steven M. Nowick (Columbia University) *65- BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems Amirhossein Mirhosseini (University of Michigan), Mohammad Sadrosadati, Behnaz Soltani, Hamid Sarbazi-Azad (Sharif university of Technology) and Thomas Wenisch (University of Michigan) |
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| Coffee Break | ||
| Panel Discussion: Networks-on-Chip: Past, Present and Future
Moderators: Umit Ogras (Arizona State University) and Zhonghai Lu (KTH Royal Institute of Technology) Panelists: - Luca Carloni (Columbia University, USA) - Ahmed Hemani (KTH Royal Institute of Technology, Sweden) - Nanni de Micheli (EPFL, Switzerland) - Vijaykrishnan Narayanan (Pennsylvania State University, USA) - Partha Pande (Washington State University, USA) - Axel Jantsch (TU Wien) |
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| Banquet | ||
| Friday October 20, 2017 | ||
| Time | ||
| Breakfast | ||
| Special Session 1: Driving Networks from Chips to Vehicles
Session chair: Zhonghai Lu (KTH Royal Institute of Technology) - Addressing Extensibility and Fault Tolerance in CAN-based Automotive Systems Hengyi Liang, Zhilu Wang, Bowen Zheng, Qi Zhu (University of California, Riverside) - JAMS: Jitter-aware Message Scheduling for FlexRay Automotive Networks Vipin Kumar Kukkala, Sudeep Pasricha (Organizer), Thomas Bradley (Colorado State University) - Design with Hybrid Automotive In-Vehicle Networks Debayan Roy, Michael Balszun, Dip Goswami, Samarjit Chakraborty (TU Eindhoven) |
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| Coffee Break | ||
| Session 3: QoS and Application Mapping
Session chair: Ahmed Hemani (KTH Royal Institute of Technology) 23 Fairness-Oriented and Location-Aware NUCA for Many-Core SoC Zicong Wang, Xiaowen Chen, Chen Li and Yang Guo (National University of Defense Technology) 40 On the Accuracy of Stochastic Delay Bound for Network on Chip Gaoming Du, Yongliang Zhang, Guanyu Liu, Zhenmin Li, Duoli Zhang and Yiming Ouyang (Hefei University of Technology) 10 SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers Hossein Farrokhbakht, Hadi Mardani Kamali and Shaahin Hessabi (Sharif University of Technology) 7 On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC Bing Li, Xiaohang Wang (South China University of Technology ), Amit Kumar Singh (University of Southampton) and Terrence Mak (The Chinese University of Hong Kong) |
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| Lunch | ||
| Session 4: NoC design for 3D stacking and neural networks
Session chair: Vassos Soteriou (Cyprus University of Technology) 32 XYZ-Randomization using TSVs for Low-Latency Energy-Efficient 3D-NoCs Hiroshi Nakahara, Nguyen Anh Vu Doan, Ryota Yasudo and Hideharu Amano (Keio University) 53 3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs Biresh Joardar, Wonje Choi (Washington State University), Ryan Kim (Carnegie Mellon University), Jana Doppa, Partha Pande (Washington State University), Diana Marculescu and Radu Marculescu (Carnegie Mellon University) 12 Rethinking NoCs for Spatial Neural Network Accelerators Hyoukjun Kwon, Ananda Samajdar and Tushar Krishna (Georgia Institute of Technology) |
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| Coffee Break | ||
| Special Session 2: Adaptive Manycore Architectures for Big Data Computing
Session chair: Partha Pande (Washington State University, USA) Adaptive Manycore Architectures for Big Data Computing Contributors: - Janardhan Rao Doppa (Washington State University) - Ryan Kim (Carnegie Mellon University) - Mihailo Isakov and Michel A. Kinsy (Boston University) - HyoukJun Kwon and Tushar Krishna (Georgia Institute of Technology) |
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| Closing Remark | ||
Keynote Talk
Speaker
Robert Zak (Intel)
Title
Networks Off Chip: High performance Fabrics in support of the Data Center Computer
AbstractWarehouse scale compute systems are increasingly being used to support HPC and HPC-like (e.g. machine learning training) "scalable workloads". The required tight coupling of compute functions, DRAM, and NVM resources over scales of 100's of meters, and thousands of fabric endpoints has driven continued innovation in data center Fabrics, including Intel's OmniPath Architecture. In this talk, I will look at the challenges associated with building these "off-chip" networks, as well as the implications, challenges, and interactions with on-board, on-package, and on-die networks. |
Biography |
Bob Zak is an Intel Fellow and the lead architect for Intel® Omni-Path Architecture in the Data Center Group at Intel Corporation. He leads the development of Intel’s next-generation fabrics, which are targeted toward high-performance, scalable computing systems for demanding applications such as scientific computing, machine learning, data analytics and storage clusters. A specialist in high-performance computer networking fabrics, Zak joined Intel in 2006. Before stepping into his current role in 2012, he spent several years as senior principal engineer in Intel’s pathfinding and architecture business unit. His work there included two-level memory architecture, non-volatile memory architecture and most recently, microserver platform architecture. Before joining Intel, Zak was a distinguished engineer at Sun Microsystems Inc. During his 10-year tenure at Sun, he contributed to networking strategy and served as an architect for UltraSPARC I/O, InfiniBand technology and scalable distributed cache architectures for enterprise servers. Earlier in his career, Zak spent 10 years working in and eventually leading the network architecture program at Thinking Machines Corp. Zak earned a combined bachelor’s and master’s degree in electrical engineering and computer science from the Massachusetts Institute of Technology. |
