Keynote Talk

Speaker

Robert Zak (Intel)

Title

Networks Off Chip: High performance Fabrics in support of the Data Center Computer

Abstract

Warehouse scale compute systems are increasingly being used to support HPC and HPC-like (e.g. machine learning training) "scalable workloads". The required tight coupling of compute functions, DRAM, and NVM resources over scales of 100's of meters, and thousands of fabric endpoints has driven continued innovation in data center Fabrics, including Intel's OmniPath Architecture. In this talk, I will look at the challenges associated with building these "off-chip" networks, as well as the implications, challenges, and interactions with on-board, on-package, and on-die networks.

Biography

Bob Zak is an Intel Fellow and the lead architect for Intel® Omni-Path Architecture in the Data Center Group at Intel Corporation. He leads the development of Intel’s next-generation fabrics, which are targeted toward high-performance, scalable computing systems for demanding applications such as scientific computing, machine learning, data analytics and storage clusters.

A specialist in high-performance computer networking fabrics, Zak joined Intel in 2006. Before stepping into his current role in 2012, he spent several years as senior principal engineer in Intel’s pathfinding and architecture business unit. His work there included two-level memory architecture, non-volatile memory architecture and most recently, microserver platform architecture.

Before joining Intel, Zak was a distinguished engineer at Sun Microsystems Inc. During his 10-year tenure at Sun, he contributed to networking strategy and served as an architect for UltraSPARC I/O, InfiniBand technology and scalable distributed cache architectures for enterprise servers. Earlier in his career, Zak spent 10 years working in and eventually leading the network architecture program at Thinking Machines Corp.

Zak earned a combined bachelor’s and master’s degree in electrical engineering and computer science from the Massachusetts Institute of Technology.

Panel Discussion

Title

Networks-on-Chip: Past, Present and Future

Abstract

  Networks-on-chip have emerged as the de-facto communication paradigm for on-chip parallel distributed computing. However, overcoming the critical challenges we faced in scaling up the computational power and addressing the limitations imposed by Moore and Denard laws are not easy. For the last 15 years, we witnessed a tremendous revolution in the mathematical models, algorithms and design methodologies developed for NoC-based multicore platforms. Consequently, instead of integrating a few cores we now aim to interconnect hundreds to thousands of processing elements through an NoC environment. Entering the Internet-of-things revolution calls for for restructuring the knowledge learned, discovering and developing more scalable design methodologies to tackle the new challenges of dealing with big data and embedding intelligence within future smart infrastructure.

  In this anniversary NOCS special session, pioneers, top thinkers and original scientists will review the success stories of NoC design, will discuss the main challenges that lie ahead of us, and provide inspiring visions for how NoC-based multicores can revolutionize all aspects of life from efficient highly accurate healthcare architectures to intelligent energy systems, from smart infrastructure and transportation to smart cities. This unique event is meant to stimulate a burst of creativity from the NOCS community to embark and solve the critical challenges our society faces.

Moderator

Paul Bogdan (University of Southern California, USA)

Panelists

  • Luca Carloni (Columbia University, USA)
  • Nanni de Micheli (EPFL, Switzerland)
  • Ahmed Hemani (KTH Royal Institute of Technology, Sweden)
  • Vijaykrishnan Narayanan (Pennsylvania State University, USA)
  • Partha Pande (Washington State University, USA)
  • Sudhakar Yalamanchili (Georgia Tech., USA)

Sponsors