業績

最近の主要な業績は以下の通り。論文リストはここにあります。

論文誌

  • Keisuke Sugiura, Hiroki Matsutani, “An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning”, IEEE Transactions on Computers (TC), Vol.xx, No.xx, 2024. [Open Access]
  • Kazuki Sunaga, Masaaki Kondo, Hiroki Matsutani, “Addressing Gap between Training Data and Deployed Environment by On-Device Learning”, IEEE Micro, Nov/Dec 2023. [Open Access]
  • Keisuke Sugiura, Hiroki Matsutani, “A Universal LiDAR SLAM Accelerator System on Low-cost FPGA”, IEEE Access, Vol.10, pp.26931-26947, Mar 2022. [Open Access]
  • Rei Ito, Mineto Tsukada, Hiroki Matsutani, “An On-Device Federated Learning Approach for Cooperative Model Update between Edge Devices”, IEEE Access, Vol.9, pp.92986-92998, Jun 2021. [Open Access]
  • Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, “A Neural Network-Based On-device Learning Anomaly Detector for Edge Devices”, IEEE Transactions on Computers (TC), Vol.69, No.7, pp.1027-1044, Jul 2020. (Featured Paper in July 2020) [Open Access]
  • Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano, “Designing High-Performance Interconnection Networks with Host-Switch Graphs”, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.30, No.2, pp.315-330, Feb 2019.
  • Shin Morishima, Hiroki Matsutani, “High-Performance with an In-GPU Graph Database Cache”, IEEE IT Professional, Special Issue on Graph Databases and Their Applications, Vol.19, No.6, pp.58-64, Nov/Dec 2017.
  • Yuta Tokusashi, Hiroki Matsutani, “Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches”, IEEE Micro, Vol.37, No.5, pp.44-51, Sep/Oct 2017.
  • Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, “Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers”, IEEE Transactions on Computers (TC), Vol.66, No.4, pp.702-716, Apr 2017.
  • Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, “Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24, No.2, pp.493-506, Feb 2016.
  • Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, “A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface”, ACM SIGARCH Computer Architecture News (CAN), Vol.43, No.4, pp.22-27, Sep 2015.
  • Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, “Swap-and-randomize: A Method for Building Low-latency HPC Interconnects”, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.26, No.7, pp.2051-2060, Jul 2015.
  • Shin Morishima, Hiroki Matsutani, “Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries”, ACM SIGARCH Computer Architecture News (CAN), Vol.42, No.4, pp.75-80, Sep 2014.
  • Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, “3D NoC with Inductive-Coupling Links for Building-Block SiPs”, IEEE Transactions on Computers (TC), Vol.63, No.3, pp.748-763, Mar 2014.
  • Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, “A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface”, IEEE Micro, Vol.33, No.6, pp.6-15, Dec 2013.
  • Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki, “Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems”, IEEE Micro, Vol.32, No.6, pp.52-61, Dec 2012.
  • Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, “Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors”, IEEE Transactions on Computers (TC), Vol.60, No.6, pp.783-799, Jun 2011.
  • Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, “Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.30, No.4, pp.520-533. Apr 2011.
  • Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano, “Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network”, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.20, No.8, pp.1126-1141, Aug 2009.

国際会議

  • Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova, “Sparse 3-D NoCs with Inductive Coupling”, Proc. of the 56th Design Automation Conference (DAC’19), pp.49:1-49:6, Jun 2019.
  • Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi, “High-Bandwidth Low-Latency Approximate Interconnection Networks”, Proc. of the 23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA’17), pp.469-480, Feb 2017.
  • Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova, “Augmenting Low-latency HPC Network with Free-space Optical Links”, Proc. of the 21st IEEE International Symposium on High-Performance Computer Architecture (HPCA’15), pp.390-401, Feb 2015.
  • Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano, “Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips”, Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE’14), pp.1-6, Mar 2014.
  • Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova, “Layout-conscious Random Topologies for HPC Off-chip Interconnects”, Proc. of the 19th IEEE International Symposium on High-Performance Computer Architecture (HPCA’13), pp.484-495, Feb 2013.
  • Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova, “A Case for Random Shortcut Topologies for HPC Interconnects”, Proc. of the 39th ACM/IEEE International Symposium on Computer Architecture (ISCA’12), pp.177-188, Jun 2012.
  • Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, “Prediction Router: Yet Another Low Latency On-Chip Router Architecture”, Proc. of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA’09), pp.367-378, Feb 2009.

受賞

  • “IEEE TC Award for Editorial Service and Excellence” (2021).
  • “Best Paper Award”, The 8th International Symposium on Computing and Networking (CANDAR’20).
  • “IPSJ Microsoft Informatics Research Award” (2018).
  • “Best Paper Award”, The 6th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART’15).
  • “Best Paper Award”, The 18th Asia and South Pacific Design Automation Conference (ASP-DAC’13).
  • “IEEE Computer Society Japan Chapter Young Author Award” (2009).