[English / Japanese]

Hiroki Matsutani


慶應義塾大学 理工学部 情報工学科 教授


最新ニュース: [松谷研トップページ]
YouTube Channel: [Matsutani Lab]
Google Scholar Citations: [Hiroki Matsutani]
Research Topics: Computer Architecture, Interconnection Networks, Machine Learning, Big Data Processing
(Last updated 2024-03-22)

経歴

論文誌
  1. Keisuke Sugiura, Hiroki Matsutani, "An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning", IEEE Transactions on Computers (TC), Vol.xx, No.xx, pp.xxx-xxx, 2024. [Open Access]
  2. Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani, "Federated Learning of Neural ODE Models with Different Iteration Counts", IEICE Transactions on Information and Systems, Vol.E107-D, No.6, pp.xxx-xxx, 2024. (to appear)
  3. Kazuki Sunaga, Takeya Yamada, Hiroki Matsutani, "A Sequential Approach to Detect Drifts and Retrain Neural Networks on Resource-Limited Edge Devices", IEICE Transactions on Information and Systems, Vol.E107-D, No.6, pp.xxx-xxx, 2024. (to appear)
  4. Kazuki Sunaga, Masaaki Kondo, Hiroki Matsutani, "Addressing Gap between Training Data and Deployed Environment by On-Device Learning", IEEE Micro, Special Issue on tinyML, Vol.43, No.6, pp.66-73, Nov/Dec 2023. [Open Access]
  5. Kenji Nemoto, Hiroki Matsutani, "A Lightweight Reinforcement Learning Based Packet Routing Method using Online Sequential Learning", IEICE Transactions on Information and Systems, Vol.E106-D, No.11, pp.1796-1807, Nov 2023. [Paper]
  6. Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani, "A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs", IEICE Transactions on Information and Systems, Vol.E106-D, No.7, pp.1186-1197, Jul 2023. [Paper]
  7. Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Designing Low-Diameter Interconnection Networks with Multi-Ported Host-Switch Graphs", Concurrency and Computation: Practice and Experience, Vol.35, No.11, p.e6115, May 2023.
  8. Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi, "A Traffic-Aware Memory-Cube Network using Bypassing", Microprocessors and Microsystems, Vol.90, No.104471, Apr 2022.
  9. Keisuke Sugiura, Hiroki Matsutani, "A Universal LiDAR SLAM Accelerator System on Low-cost FPGA", IEEE Access, Vol.10, pp.26931-26947, Mar 2022. [Open Access]
  10. Mineto Tsukada, Hiroki Matsutani, "An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms, Vol.E105-A, No.3, pp.437-447, Mar 2022. [Paper]
  11. Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs", IEICE Transactions on Information and Systems, Special Section on Parallel, Distributed, Reconfigurable Computing, and Networking, Vol.E104-D, No.12, pp.2057-2067, Dec 2021. [Paper]
  12. Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani, "An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning", International Journal of Networking and Computing (IJNC), Special Issue on the International Symposium on Computing and Networking, Vol.11, No.2, pp.516-532, Jul 2021. [Open Access]
  13. Rei Ito, Mineto Tsukada, Hiroki Matsutani, "An On-Device Federated Learning Approach for Cooperative Model Update between Edge Devices", IEEE Access, Vol.9, pp.92986-92998, Jun 2021. [Open Access]
  14. Keisuke Sugiura, Hiroki Matsutani, "An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm", IEICE Transactions on Information and Systems, Vol.E104-D, No.6, pp.789-800, Jun 2021. [Paper]
  15. Takuya Sakuma, Hiroki Matsutani, "An Area-Efficient Recurrent Neural Network Core for Unsupervised Time-Series Anomaly Detection", IEICE Transactions on Electronics, Special Section on Low-Power and High-Speed Chips, Vol.E104-C, No.6, pp.247-256, Jun 2021. [Paper]
  16. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks", IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Vol.E103-D, No.12, pp.2471-2479, Dec 2020.
  17. Shin Morishima, Hiroki Matsutani, "In-GPU Cache for Acceleration of Anomaly Detection in Blockchain", IEICE Transactions on Information and Systems, Vol.E103-D, No.8, pp.1814-1824, Aug 2020.
  18. Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, "A Neural Network-Based On-device Learning Anomaly Detector for Edge Devices", IEEE Transactions on Computers (TC), Vol.69, No.7, pp.1027-1044, Jul 2020. (Featured Paper in July 2020 Issue of IEEE TC) [Open Access]
  19. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks", IEICE Transactions on Information and Systems, Vol.E103-D, No.1, pp.101-110, Jan 2020.
  20. Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani, "An FPGA-Based Change-Point Detection for 10Gbps Packet Stream", IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Vol.E102-D, No.12, pp.2366-2376, Dec 2019. [Paper]
  21. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano, "Designing High-Performance Interconnection Networks with Host-Switch Graphs", IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.30, No.2, pp.315-330, Feb 2019.
  22. Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "Proxy Responses by FPGA-based Switch for MapReduce Stragglers", IEICE Transactions on Information and Systems, Vol.E101-D, No.9, pp.2258-2268, Sep 2018. [Paper]
  23. Yuma Sakakibara, Shin Morishima, Kohei Nakamura, Hiroki Matsutani, "A Hardware-Based Caching System on FPGA NIC for Blockchain", IEICE Transactions on Information and Systems, Vol.E101-D, No.5, pp.1350-1360, May 2018. [Paper]
  24. Akio Nomura, Hiroki Matsutani, Yusuke Matsushita, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano, "Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface", International Journal of Networking and Computing (IJNC), Vol.8, No.1, pp.124-139, Jan 2018.
  25. Shin Morishima, Hiroki Matsutani, "High-Performance with an In-GPU Graph Database Cache", IEEE IT Professional, Special Issue on Graph Databases and Their Applications, Vol.19, No.6, pp.58-64, Nov/Dec 2017.
  26. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Layout-Oriented Routing Method for Low-Latency HPC Networks", IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Vol.E100-D, No.12, pp.2796-2807, Dec 2017.
  27. Yuta Tokusashi, Hiroki Matsutani, "Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches", IEEE Micro, Vol.37, No.5, pp.44-51, Sep/Oct 2017. (電気通信普及財団 テレコムシステム技術学生賞)
  28. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing", IEICE Transactions on Information and Systems, Vol.E100-D, No.8, pp.1798-1806, Aug 2017.
  29. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, "Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers", IEEE Transactions on Computers (TC), Vol.66, No.4, pp.702-716, Apr 2017. (電気通信普及財団 テレコムシステム技術学生賞)
  30. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface", IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Vol.E99-D, No.12, pp.2871-2880, Dec 2016.
  31. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems", IEICE Transactions on Electronics, Special Section on Low-Power and High-Speed Chips, Vol.E99-C, No.8, pp.909-917, Aug 2016.
  32. Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh, "Optical Network Technologies for HPC: Computer-Architects Point of View", IEICE Electronics Express, Vol.13, No.6, pp.1-14, Mar 2016.
  33. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, "Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24, No.2, pp.493-506, Feb 2016.
  34. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface", ACM SIGARCH Computer Architecture News (CAN), Vol.43, No.4, pp.22-27, Sep 2015. [Paper]
  35. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, "Swap-and-randomize: A Method for Building Low-latency HPC Interconnects", IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.26, No.7, pp.2051-2060, Jul 2015.
  36. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries", ACM SIGARCH Computer Architecture News (CAN), Vol.42, No.4, pp.75-80, Sep 2014. [Paper]
  37. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "3D NoC with Inductive-Coupling Links for Building-Block SiPs", IEEE Transactions on Computers (TC), Vol.63, No.3, pp.748-763, Mar 2014.
  38. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs", IPSJ Transactions on System LSI Design Methodology (T-SLDM), Vol.7, pp.27-36, Feb 2014.
  39. Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface", IEEE Micro, Vol.33, No.6, pp.6-15, Dec 2013.
  40. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, "Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs", IEICE Transactions on Information and Systems, Vol.E96-D, No.12, pp.2753-2764, Dec 2013.
  41. Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki, "Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems", IEEE Micro, Vol.32, No.6, pp.52-61, Dec 2012.
  42. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip", International Journal of Networking and Computing (IJNC), Vol.1, No.2, pp.244-259, Jul 2011.
  43. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors", IEEE Transactions on Computers (TC), Vol.60, No.6, pp.783-799, Jun 2011.
  44. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.30, No.4, pp.520-533. Apr 2011.
  45. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Semi-deflection Routing: A Non-minimal Fully-adaptive Routing for Virtual Cut-through Switching Network", International Journal of Computer and Network Security (IJCNS), Vol.2, No.10, pp.52-58, Oct 2010.
  46. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano, "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.20, No.8, pp.1126-1141, Aug 2009. (IEEE Computer Society Japan Chapter Young Author Award)
  47. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs", IEICE Transactions on Information and Systems, Vol.E92-D, No.4, pp.575-583, Apr 2009.
  48. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs", IEICE Transactions on Information and Systems, Vol.E90-D, No.12, pp.1914-1922, Dec 2007.

国際会議
  1. Kazuki Sunaga, Keisuke Sugiura, Hiroki Kawakami, Hiroki Matsutani, "An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm", Proc. of the 38th IEEE International Parallel and Distributed Processing Symposium (IPDPS'24) Workshops, The 31st Reconfigurable Architectures Workshop (RAW'24), pp.xxx-xxx, May 2024. (to appear)
  2. Yujiro Yahata, Keisuke Sugiura, Hiroki Matsutani, "A Scalable Secure Fault Tolerant Aggregation for P2P Federated Learning", Proc. of the 38th IEEE International Parallel and Distributed Processing Symposium (IPDPS'24) Workshops, The 26th Workshop on Advances in Parallel and Distributed Computational Models (APDCM'24), pp.xxx-xxx, May 2024.
  3. Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani, "Performance Improvement of Federated Learning Server using Smart NIC", Proc. of the 11th International Symposium on Computing and Networking (CANDAR'23) Workshops, The 6th Sustainable Computing Systems Workshop (SUSCW'23), pp.165-171, Nov 2023. [Paper]
  4. Takeya Yamada, Hiroki Matsutani, "A Lightweight Concept Drift Detection Method for On-Device Learning on Resource-Limited Edge Devices", Proc. of the 37th IEEE International Parallel and Distributed Processing Symposium (IPDPS'23) Workshops, The 5th Workshop on Parallel AI and Systems for the Edge (PAISE'23), pp.761-768, May 2023. [Paper] [Slide]
  5. Ikumi Okubo, Keisuke Sugiura, Hiroki Kawakami, Hiroki Matsutani, "A Lightweight Transformer Model using Neural ODE for FPGAs", Proc. of the 37th IEEE International Parallel and Distributed Processing Symposium (IPDPS'23) Workshops, The 30th Reconfigurable Architectures Workshop (RAW'23), pp.105-112, May 2023. [Paper]
  6. Mizuki Yasuda, Keisuke Sugiura, Ryuto Kojima, Hiroki Matsutani, "An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs", Proc. of the 37th IEEE International Parallel and Distributed Processing Symposium (IPDPS'23) Workshops, The 30th Reconfigurable Architectures Workshop (RAW'23), pp.113-120, May 2023. [Paper]
  7. Keisuke Sugiura, Hiroki Matsutani, "An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs", Proc. of the 31st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'23), pp.68-75, Mar 2023. [Paper]
  8. Man Wu, Hiroki Matsutani, Masaaki Kondo, "ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC", Proc. of the 24th IEEE International Conference on High Performance Computing and Communications (HPCC'22), pp.546-553, Dec 2022.
  9. Keisuke Sugiura, Hiroki Matsutani, "P3Net: PointNet-based Path Planning on FPGA", Proc. of the 21st IEEE International Conference on Field Programmable Technology (ICFPT'22), pp.1-9, Dec 2022. [Paper]
  10. Kenji Nemoto, Hiroki Matsutani, "A Packet Routing using Lightweight Reinforcement Learning Based on Online Sequential Learning", Proc. of the 10th International Symposium on Computing and Networking (CANDAR'22) Workshops, The 10th International Workshop on Computer Systems and Architectures (CSA'22), pp.76-82, Nov 2022. [Paper]
  11. Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani, "Communication Size Reduction of Federated Learning based on Neural ODE Model", Proc. of the 10th International Symposium on Computing and Networking (CANDAR'22) Workshops, The 10th International Workshop on Computer Systems and Architectures (CSA'22), pp.55-61, Nov 2022. [Paper]
  12. Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks", Proc. of the 10th International Symposium on Computing and Networking (CANDAR'22), pp.117-123, Nov 2022.
  13. Masaki Furukawa, Hiroki Matsutani, "Accelerating Distributed Deep Reinforcement Learning by In-Network Experience Sampling", Proc. of the 30th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'22), pp.75-82, Mar 2022. [Paper] [Slide]
  14. Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani, "dsODENet: Neural ODE and Depthwise Separable Convolution for Domain Adaptation on FPGAs", Proc. of the 30th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'22), pp.152-156, Mar 2022. [Paper]
  15. Keisuke Sugiura, Hiroki Matsutani, "A Unified Accelerator Design for LiDAR SLAM Algorithms for Low-end FPGAs", Proc. of the 20th IEEE International Conference on Field Programmable Technology (ICFPT'21), pp.1-9, Dec 2021. [Paper]
  16. Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph", Proc. of the 8th International Virtual Conference on Applied Computing & Information Technology (ACIT'21), pp.51-55, Jun 2021.
  17. Hirohisa Watanabe, Hiroki Matsutani, "Accelerating ODE-Based Neural Networks on Low-Cost FPGAs", Proc. of the 35th IEEE International Parallel and Distributed Processing Symposium (IPDPS'21) Workshops, The 28th Reconfigurable Architectures Workshop (RAW'21), pp.88-95, May 2021. (Best Paper Nominee) [Paper]
  18. Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani, "An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning", Proc. of the 35th IEEE International Parallel and Distributed Processing Symposium (IPDPS'21) Workshops, The 28th Reconfigurable Architectures Workshop (RAW'21), pp.96-103, May 2021. [Paper]
  19. Keisuke Sugiura, Hiroki Matsutani, "Evaluation of Neural Network Based Scan Matching for SLAM SoC Implementations", The 24th IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24), Poster session, Apr 2021. (Poster Award)
  20. Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi, "Low-Latency Low-Energy Memory-Cube Networks Using Dual-Voltage Bypassing Datapaths", Proc. of the 29th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'21), pp.143-147, Mar 2021.
  21. Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani, "An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning", Proc. of the 8th International Symposium on Computing and Networking (CANDAR'20), pp.108-114, Nov 2020. (Best Paper Award) [Paper] [Youtube Video]
  22. Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, "Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks", Proc. of the 8th International Symposium on Computing and Networking (CANDAR'20) Workshops, The 8th International Workshop on Computer Systems and Architectures (CSA'20), pp.93-99, Nov 2020. (CSA Best Paper Award)
  23. Yang Qin, Hiroki Matsutani, Masaaki Kondo, "A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection", Proc. of the 13th IEEE International Conference on Cyber Physical and Social Computing (CPSCom'20), pp.684-691, Nov 2020.
  24. Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, Masaaki Kondo, "Fast Semi-Supervised Anomaly Detection of Drivers' Behavior Using Online Sequential Extreme Learning Machine", Proc. of the 23rd IEEE International Conference on Intelligent Transportation Systems (ITSC'20), pp.985-992, Sep 2020.
  25. Tokio Kibata, Mineto Tsukada, Hiroki Matsutani, "An Edge Attribute-wise Partitioning and Distributed Processing of R-GCN using GPUs", Proc. of the 26th International European Conference on Parallel and Distributed Computing (Euro-Par'20) Workshops, The 18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'20), pp.122-134, Aug 2020. [Paper]
  26. Takuya Sakuma, Hiroki Matsutani, "An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection", Proc. of the 23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 23), pp.1-3, Apr 2020. [Paper]
  27. Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch", Proc. of the 28th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'20), pp.102-109, Mar 2020. [Paper]
  28. Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, "Deadlock-Free Layered Routing for Infiniband Networks", Proc. of the 7th International Symposium on Computing and Networking (CANDAR'19) Workshops, The 7th International Workshop on Computer Systems and Architectures (CSA'19), pp.84-90, Nov 2019.
  29. Rei Ito, Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, "An Adaptive Abnormal Behavior Detection using Online Sequential Learning", Proc. of the 17th International Conference on Embedded and Ubiquitous Computing (EUC'19), pp.436-440, Aug 2019. [Paper]
  30. Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova, "Sparse 3-D NoCs with Inductive Coupling", Proc. of the 56th Design Automation Conference (DAC'19), pp.49:1-49:6, Jun 2019.
  31. Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, "An FPGA-based On-device Sequential Learning Approach for Unsupervised Anomaly Detection", The 27th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'19), Demo Night, Apr 2019. [Youtube Video]
  32. Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani, "Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core", Proc. of the 22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), pp.1-3, Apr 2019. [Paper]
  33. Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano, "Key-value Store Chip Design for Low Power Consumption", Proc. of the 22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), pp.1-3, Apr 2019. [Paper]
  34. Shin Morishima, Hiroki Matsutani, "Acceleration of Anomaly Detection in Blockchain Using In-GPU Cache", Proc. of the 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'18), pp.244-251, Dec 2018. [Paper]
  35. Yuma Sakakibara, Yuta Tokusashi, Shin Morishima, Hiroki Matsutani, "Accelerating Blockchain Transfer System Using FPGA-Based NIC", Proc. of the 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'18), pp.171-178, Dec 2018. [Paper]
  36. Kaho Okuyama, Yuta Tokusashi, Takuma Iwata, Mineto Tsukada, Kazumasa Kishiki, Hiroki Matsutani, "Network Optimizations on Prediction Server with Multiple Predictors", Proc. of the 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'18), pp.1044-1045, Dec 2018. [Paper]
  37. Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani, "MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories", Proc. of the 17th IEEE International Conference on Field Programmable Technology (ICFPT'18), pp.134-141, Dec 2018. [Paper]
  38. Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman, "LaKe: The Power of In-Network Computing", Proc. of the 13th International Conference on ReConFigurable Computing and FPGAs (ReConFig'18), pp.1-8, Dec 2018. [Paper]
  39. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, "k-Optimized Path Routing for High-Throughput Data Center Networks", Proc. of the 6th International Symposium on Computing and Networking (CANDAR'18), pp.99-105, Nov 2018. (Outstanding Paper Award)
  40. Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "An Trace-Driven Performance Prediction Method for Exploring 3D-NoC Design Optimization", Proc. of the 6th International Symposium on Computing and Networking (CANDAR'18) Workshops, The 6th International Workshop on Computer Systems and Architectures (CSA'18), pp.182-185, Nov 2018.
  41. Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi, "Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications", Proc. of the 17th IEEE International Symposium on Network Computing and Applications (NCA'18), pp.1-10, Nov 2018.
  42. Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation", Proc. of the 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS'18), pp.1-8, Oct 2018. (Best Paper Candidate)
  43. Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Adaptive Body Bias Control Scheme for Ultra Low-power Network-on-Chip Systems", Proc. of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'18), pp.146-153, Sep 2018.
  44. Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani, "Accelerating Online Change-Point Detection Algorithm using 10 GbE FPGA NIC", Proc. of the 24th International European Conference on Parallel and Distributed Computing (Euro-Par'18) Workshops, The 16th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'18), pp.506-517, Aug 2018. [Paper]
  45. Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, "OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector", Proc. of the 24th International European Conference on Parallel and Distributed Computing (Euro-Par'18) Workshops, The 16th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'18), pp.518-529, Aug 2018. [Paper]
  46. Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Performance Evaluation of 3D-Stacked Processor under Temperature Constraints", The 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21), Poster session, Apr 2018.
  47. Shin Morishima, Hiroki Matsutani, "Accelerating Blockchain Search of Full Nodes Using GPUs", Proc. of the 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'18), pp.244-248, Mar 2018. [Paper]
  48. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies", Proc. of the 23rd IEEE International Conference on Parallel and Distributed Systems (ICPADS'17), pp.664-673, Dec 2017.
  49. Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki, "Building Block Multi-Chip Systems Using Inductive Coupling Through Chip Interface", Proc. of the 14th International SoC Design Conference (ISOCC'17), pp.152-154, Nov 2017.
  50. Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "In-Switch Approximate Processing: Delayed Tasks Management for MapReduce Applications", Proc. of the 27th International Conference on Field-Programmable Logic and Applications (FPL'17), pp.1-4, Sep 2017. [Paper]
  51. Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova, "A Case for Uni-Directional Network Topologies in Large-Scale Clusters", Proc. of the 19th IEEE International Conference on Cluster Computing (Cluster'17), pp.178-187, Sep 2017.
  52. Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Towards Tightly-coupled Datacenter with Free-space Optical Links", Proc. of the 1st International Conference on Cloud and Big Data Computing (ICCBDC'17), pp.33-39, Sep 2017. (Best Oral Presentation)
  53. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano, "Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks", Proc. of the 46th International Conference on Parallel Processing (ICPP'17), pp.322-331, Aug 2017.
  54. Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "3D layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface", Proc. of the 14th International Symposium on Pervasive Systems, Algorithms, and Networks (I-SPAN'17), pp.52-59, Jun 2017.
  55. Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani, "An FPGA NIC Based Hardware Caching for Blockchain", Proc. of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'17), pp.1:1-1:6, Jun 2017. [Paper]
  56. Shin Morishima, Masahiro Okazaki, Hiroki Matsutani, "A Case for Remote GPUs over 10GbE Network for VR Applications", Proc. of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'17), pp.19:1-19:6, Jun 2017. [Paper]
  57. Ami Hayashi, Hiroki Matsutani, "An FPGA-Based In-NIC Cache Approach for Lazy Learning Outlier Filtering", Proc. of the 25th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'17), pp.15-22, Mar 2017. [Paper]
  58. Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi, "High-Bandwidth Low-Latency Approximate Interconnection Networks", Proc. of the 23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA'17), pp.469-480, Feb 2017. [Paper]
  59. Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani, "Accelerating Spark RDD Operations with Local and Remote GPU Devices", Proc. of the 22nd IEEE International Conference on Parallel and Distributed Systems (ICPADS'16), pp.791-799, Dec 2016. [Paper]
  60. Kohei Nakamura, Ami Hayashi, Hiroki Matsutani, "An FPGA-Based Low-Latency Network Processing for Spark Streaming", Proc. of the 4th IEEE International Conference on Big Data (BigData'16) Workshops, The 1st Workshop on Real-Time and Stream Analytics in Big Data, pp.2410-2415, Dec 2016. [Paper]
  61. Akihiko Hamada, Hiroki Matsutani, "Design and Implementation of Hardware Cache Mechanism and NIC for Column-Oriented Databases", Proc. of the 11th International Conference on ReConFigurable Computing and FPGAs (ReConFig'16), pp.1-6, Nov 2016. [Paper]
  62. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "LOREN: A Scalable Routing Method for Layout-conscious Random Topologies", Proc. of the 4th International Symposium on Computing and Networking (CANDAR'16), pp.9-18, Nov 2016. (Best Paper Award)
  63. Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano, "Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface", Proc. of the 4th International Symposium on Computing and Networking (CANDAR'16), pp.195-201, Nov 2016.
  64. Yuta Tokusashi, Hiroki Matsutani, "A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches", Proc. of the 24th IEEE International Symposium on High Performance Interconnects (Hot Interconnects 24), pp.60-67, Aug 2016. [Paper]
  65. Yuta Tokusashi, Hiroki Matsutani, "NOSQL Hardware Appliance with Multiple Data Structures", The 28th IEEE Symposium on High Performance Chips (Hot Chips 28), Poster session, Aug 2016.
  66. Shin Morishima, Hiroki Matsutani, "Distributed In-GPU Data Cache for Document-Oriented Data Store via PCIe over 10Gbit Ethernet", Proc. of the 22nd International European Conference on Parallel and Distributed Computing (Euro-Par'16) Workshops, The 14th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'16), pp.41-55, Aug 2016. [Paper]
  67. Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi, "Randomly Optimized Grid Graph for Low-Latency Interconnection Networks", Proc. of the 45th International Conference on Parallel Processing (ICPP'16), pp.340-349, Aug 2016.
  68. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free", Proc. of the 15th IEEE/ACIS International Conference on Computer and Information Science (ICIS'16), pp.565-570, Jun 2016.
  69. Korechika Tamura, Hiroki Matsutani, "An In-Kernel NOSQL Cache for Range Queries Using FPGA NIC", Proc. of the 1st International Conference on FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC'16), pp.13-18, May 2016. [Paper]
  70. Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "D-TDMA Data Buses with CSMA/CD Arbitration Bus on Wireless 3D IC", Proc. of the 13th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'16), pp.242-249, Feb 2016.
  71. Daichi Fujiki, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Randomizing Packet Memory Networks for Low-latency Processor-memory Communication", Proc. of the 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'16), pp.168-175, Feb 2016.
  72. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, "On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck", Proc. of the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'15), pp.16:1-16:8, Sep 2015.
  73. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips", Proc. of the 9th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'15), pp.41-48, Sep 2015.
  74. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, "3D Shared Bus Architecture Using Inductive Coupling Interconnect", Proc. of the 9th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'15), pp.259-266, Sep 2015.
  75. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Document-Oriented Databases using GPU and Cache Structure", Proc. of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'15), pp.108-115, Aug 2015. [Paper]
  76. Seiichi Tade, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Metamorphotic Network-on-Chip for Various Types of Parallel Applications", Proc. of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'15), pp.98-105, Jul 2015.
  77. Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, "A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface", Proc. of the 6th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'15), Jun 2015. (Best Paper Award)
  78. Shin Morishima, Hiroki Matsutani, "A GPU-Based Acceleration Method for Document-Oriented Databases", The 6th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'15), Poster session, Jun 2015.
  79. Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano, "3D Bus Architecture using Inductive Coupling ThruChip-Interface", The 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr 2015.
  80. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Staggered Stacking: Connecting Many Small Chips Using ThruChip Interface", The 18th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Poster session, Apr 2015.
  81. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Optimized Core-links for Low-latency NoCs", Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'15), pp.172-176, Mar 2015.
  82. Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova, "Augmenting Low-latency HPC Network with Free-space Optical Links", Proc. of the 21st IEEE International Symposium on High-Performance Computer Architecture (HPCA'15), pp.390-401, Feb 2015. [Paper] [Slide]
  83. Shin Morishima, Hiroki Matsutani, "Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries", The 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'14), Jun 2014.
  84. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, "Skywalk: a Topology for HPC Networks with Low-delay Switches", Proc. of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS'14), pp.263-272, May 2014.
  85. Go Matsumura, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "On/Off Link Selection Schemes for Wireless 3D NoCs", The 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Apr 2014.
  86. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", The 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Apr 2014. (Featured Poster Award)
  87. Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano, "Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips", Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE'14), pp.1-6, Mar 2014. [Paper] [Slide]
  88. Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity", Proc. of the International Symposium on Advances of Distributed and Parallel Computing (ADPC'13), pp.77-85, Dec 2013.
  89. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, "Performance Degradation by Deactivated Cores in 2-D Mesh NoCs", Proc. of the 7th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'13), pp.25-30, Sep 2013.
  90. Yusuke Kumura, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki, "A Low-Power Link Speed Control Method on Distributed Real-time Systems", Proc. of the 7th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'13), pp.49-54, Sep 2013.
  91. Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usam, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface", The 25th IEEE Symposium on High Performance Chips (Hot Chips 25), Poster session, Aug 2013.
  92. Daisuke Sasaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Deadlock-Free Routing Strategy for Stacking 3-D NoCs with Different Topologies", The 4th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'13), Poster session, Jun 2013.
  93. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture", Proc. of the 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'13), pp.29-36, Apr 2013. [Paper]
  94. Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface", Proc. of the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), pp.1-3, Apr 2013.
  95. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive-Coupling Links", Proc. of the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), pp.1-3, Apr 2013.
  96. Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "Performance and Energy Optimization of a Heterogeneous Multi-Core Processor with Inductive Coupling Links", The 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Poster session, Apr 2013. (Best Poster Award)
  97. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Low Latency Network Topology Using Multiple Links at Each Host", The 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Poster session, Apr 2013.
  98. Osamu Yoshizumi, Hiroki Matsutani, Nobuyuki Yamasaki, "Packet Routing for Distributed Real-Time System on Real-Time Communication Link", Proc. of the 28th ISCA International Conference on Computers and Their Applications (CATA'13), pp.197-204, Mar 2013.
  99. Kazutoshi Suito, Masayoshi Takasu, Rikuhei Ueda, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki, "Experimental Evaluation of Low Power Techniques on Dependable Responsive Multithreaded Processor", Proc. of the 28th ISCA International Conference on Computers and Their Applications (CATA'13), pp.281-288, Mar 2013.
  100. Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova, "Layout-conscious Random Topologies for HPC Off-chip Interconnects", Proc. of the 19th IEEE International Symposium on High-Performance Computer Architecture (HPCA'13), pp.484-495, Feb 2013. [Paper] [Slide]
  101. Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "A Case for Wireless 3D NoCs for CMPs", Proc. of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), pp.23-28, Jan 2013. (Best Paper Award) [Paper] [Slide]
  102. Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "Dynamic Power Control with a Heterogeneous Multi-Core System Using A 3-D Wireless Inductive Coupling Interconnect", Proc. of the 11th IEEE International Conference on Field Programmable Technology (ICFPT'12), Demo session, pp.293-296, Dec 2012.
  103. Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, "Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router", Proc. of the 6th IEEE International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'12), pp.59-66, Sep 2012.
  104. Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, "CMA-Cube: A Scalable Reconfigurable Accelerator with 3-D Wireless Inductive Coupling Interconnect", Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL'12), pp.543-546, Aug 2012.
  105. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova, "A Case for Random Shortcut Topologies for HPC Interconnects", Proc. of the 39th ACM/IEEE International Symposium on Computer Architecture (ISCA'12), pp.177-188, Jun 2012. [Paper] [Slide]
  106. Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki, "Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems", Proc. of the 15th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XV), pp.1-3, Apr 2012.
  107. Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "An Extension of Real-Time OS for Multithreaded Processors", Proc. of the 18th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'12), Work-In-Progress session, Apr 2012.
  108. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, "Vertical Link On/Off Control Methods for Wireless 3-D NoCs", Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS'12), pp.212-224, Feb 2012.
  109. Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs", Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC'12), pp.407-412, Jan 2012. (Best Paper Candidate) [Paper] [Slide]
  110. Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, "Performance Evaluation of Power-aware Multi-tree Ethernet for HPC Interconnects", Proc. of the 2nd International Conference on Networking and Computing (ICNC'11), pp.50-57, Nov 2011. (Best Paper Award) [Paper] [Slide]
  111. Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki, "Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor", Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), pp.9-15, Aug 2011.
  112. Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki, "Design and Implementation of On-chip Adaptive Router with Predictor for Regional Congestion", Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), pp.22-27, Aug 2011.
  113. Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano, "A Dynamic Link-Width Optimization for Network-on-Chip", Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), pp.106-108, Aug 2011.
  114. Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs", Proc. of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11), pp.49-56, May 2011. [Paper] [Slide]
  115. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Variable-pipeline On-chip Router Optimized to Traffic Pattern", Proc. of the 3rd International Workshop on Network on Chip Architectures (NoCArc'10), pp.57-62, Dec 2010.
  116. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutumo Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip", Proc. of the 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS'10), pp.156-161, Nov 2010.
  117. Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks", Proc. of the 5th IEEE International Conference on Networking, Architecture, and Storage (NAS'10), pp.218-227, Jul 2010. [Paper] [Slide]
  118. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "A Deadlock-free Non-minimal Fully Adaptive Routing using Virtual Cut-through Switching", Proc. of the 5th IEEE International Conference on Networking, Architecture, and Storage (NAS'10), pp.431-438, Jul 2010.
  119. Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Yusuke Umahashi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "A Multi-Vdd Variable-Pipeline On-Chip Router for CMPs", The 24th ACM International Conference on Supercomputing (ICS'10), Poster session, Jun 2010.
  120. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, "Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs", Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), pp.61-68, May 2010. [Paper] [Slide]
  121. Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Low-Power Fault-Tolerant NoC using Error Correction and Detection Codes", Proc. of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'10), pp.111-118, Feb 2010.
  122. Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Performance, Cost, and Power Evaluations of On-Chip Network Topologies in FPGAs", Proc. of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN'10), pp.181-189, Feb 2010.
  123. Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, "Balanced Dimension-Order Routing for k-ary n-cubes", Proc. of the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'09), CD-ROM, Sep 2009.
  124. Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano, "MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link", Proc. of the 19th International Conference on Field Programmable Logic and Applications (FPL'09), pp.6-11, Sep 2009.
  125. Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, "An On/Off Link Activation Method for Power Regulation in InfiniBand", Proc. of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'09), pp.289-295, Jun 2009.
  126. Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano, "An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters", Proc. of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS'09), CD-ROM, May 2009. [Paper] [Slide]
  127. Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano, "Evaluation of a Multi-core Reconfigurable Architecture with Variable Core Size", Proc. of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS'09) Workshops, The 16th Reconfigurable Architectures Workshop (RAW'09), CD-ROM, May 2009.
  128. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Low-Power Variable-Pipeline Router using Pipeline-Stage Integration", The 12th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips XII), Poster session, Apr 2009.
  129. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, "Prediction Router: Yet Another Low Latency On-Chip Router Architecture", Proc. of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA'09), pp.367-378, Feb 2009. [Paper] [Slide]
  130. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems", Proc. of the 18th International Conference on Field Programmable Logic and Applications (FPL'08), pp.269-274, Sep 2008.
  131. Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano, "Three-Dimensional Layout of On-Chip Tree-Based Networks", Proc. of the 9th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'08), pp.281-288, May 2008. [Paper] [Slide]
  132. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks", Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08), pp.23-32, Apr 2008. [Paper] [Slide]
  133. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston, "A Lightweight Fault-tolerant Mechanism for Network-on-chip", Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08), pp.13-22, Apr 2008. [Paper] [Slide]
  134. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing", Proc. of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC'08), pp.55-60, Jan 2008. [Paper] [Slide]
  135. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Tightly-Coupled Multi-Layer Topologies for 3-D NoCs", Proc. of the 36th International Conference on Parallel Processing (ICPP'07), CD-ROM, Sep 2007. [Paper] [Slide]
  136. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems", Proc. of the 17th International Conference on Field Programmable Logic and Applications (FPL'07), pp.383-388, Aug 2007.
  137. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "XNoTs: Crossbar-Connected Multi-Layer Topologies for 3-D NoCs", The 10th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips X), Poster session, Apr 2007. [Poster]
  138. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", Proc. of the 21st IEEE International Parallel and Distributed Processing Symposium (IPDPS'07), CD-ROM, Mar 2007. [Paper] [Slide]
  139. Hiroki Matsutani, "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", The 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), Student Forum, Jan 2007. (Young Student Award) [Poster]
  140. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Enforcing Dimension-Order Routing in On-Chip Torus Networks without Virtual Channels", Proc. of the 4th International Symposium on Parallel and Distributed Processing and Applications (ISPA'06), pp.207-218, Dec 2006. [Paper]
  141. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks", Proc. of the 19th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS'06), pp.24-31, Sep 2006. [Paper]
  142. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano, "A Parametric Study of Scalable Interconnects on FPGAs", Proc. of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'06), pp.130-135, Jun 2006.
  143. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Kenichiro Anjo, Toru Awashima, Hideharu Amano, "An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor", Proc. of the 4th IEEE International Conference on Field Programmable Technology (ICFPT'05), pp.163-170, Dec 2005.
  144. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips", Proc. of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'05), pp.1343-1349, Jun 2005. [Paper]
  145. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano, "Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips", Proc. of the 34th International Conference on Parallel Processing (ICPP'05) Workshops, The 2nd International Workshop on Embedded Computing (ICPP-EC'05), pp.273-280, Jun 2005. [Paper] [Slide]
  146. Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai, "Mobile Gateways for Mobile Ad-hoc Networks with Network Mobility Support", Proc. of the 4th International Conference on Networking (ICN'05), pp.361-368, Apr 2005.
  147. Hiroki Matsutani, Ryuji Wakikawa, Koshiro Mitsuya, Jun Murai, "Performance Oriented Management System for Reconfigurable Network Appliances", Proc. of the 1st International Workshop on Networked Sensing Systems (INSS'04), pp.129-133, Jun 2004. [Paper]
  148. Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai, "Mobile Gateway: Integration of MANET and NEMO", The 5th ACM International Symposium on Mobile Ad Hoc Networking and Computing (MobiHoc'04), Poster session, May 2004.

国内研究会 (Since 2020)
  1. 須永 一輝, 杉浦 圭祐, 松谷 宏紀, "逐次学習可能なグラフ分散表現のFPGAアクセラレータ", 電子情報通信学会技術研究報告 CPSY2023-35, Vol.123, No.293, pp.48-53, Dec 2023.
  2. 八幡 悠二郎, 杉浦 圭祐, 松谷 宏紀, "Peer-to-Peer連合学習における難読化モデル交換の通信量削減", 電子情報通信学会技術研究報告 CPSY2023-10 (SWoPP'23), Vol.123, No.145, pp.13-18, Aug 2023. (電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞)
  3. 杉浦 圭祐, 小島 瑠斗, 松谷 宏紀, "点群特徴抽出のFPGAによる高速化", 電子情報通信学会技術研究報告 CPSY2022-44 (ETNET'23), Vol.122, No.451, pp.60-65, Mar 2023. (情報処理学会 コンピュータサイエンス領域奨励賞)
  4. 小島 瑠斗, 杉浦 圭祐, 松谷 宏紀, "強化学習を用いた3D LiDAR SLAM向け入力点群削減手法", 電子情報通信学会技術研究報告 CPSY2022-47 (ETNET'23), Vol.122, No.451, pp.77-82, Mar 2023.
  5. 伊藤 響, 松谷 宏紀, "OS-ELMを用いたオンライン逐次型グラフ分散表現学習法", 電子情報通信学会技術研究報告 CPSY2022-48 (ETNET'23), Vol.122, No.451, pp.83-88, Mar 2023.
  6. 大久保 郁海, 杉浦 圭祐, 川上 大輝, 松谷 宏紀, "Neural ODEを用いたFPGA向け高効率マルチヘッド自己注意機", 電子情報通信学会技術研究報告 CPSY2022-27, Vol.122, No.328, pp.1-6, Jan 2023.
  7. 安田 瑞生, 小島 瑠斗, 杉浦 圭祐, 松谷 宏紀, "エッジ-サーバ協調型LiDAR SLAMのFPGAへのオフロード手法", 電子情報通信学会技術研究報告 CPSY2022-28, Vol.122, No.328, pp.7-12, Jan 2023.
  8. 柴原 尚紀, 星野 優斗, 松谷 宏紀, "スマートNICを用いた連合学習の集約処理高速化の検討", 電子情報通信学会技術研究報告 CPSY2022-32, Vol.122, No.328, pp.23-28, Jan 2023. (情報処理学会 システム・アーキテクチャ研究会 若手奨励賞)
  9. 須永 一輝, 吉田 康太, 松谷 宏紀, "無線センサノード向けオンデバイス学習の信頼性向上手法", 電子情報通信学会技術研究報告 CPSY2022-33, Vol.122, No.328, pp.29-34, Jan 2023.
  10. 山田 赳也, 松谷 宏紀, "オンライン逐次学習のための軽量コンセプトドリフト検知手法", 電子情報通信学会技術研究報告 CPSY2022-19, Vol.122, No.204, pp.8-13, Oct 2022.
  11. 塚田 峰登, 近藤 正章, 松谷 宏紀, "無線センサノードを対象としたオンデバイス学習の異常検知への応用", 電子情報通信学会技術研究報告 CPSY2022-10 (SWoPP'22), Vol.122, No.133, pp.53-58, Jul 2022. (情報処理学会 システム・アーキテクチャ研究会 若手奨励賞)
  12. 根本 研司, 松谷 宏紀, "オンライン逐次学習を用いた軽量強化学習によるパケットルーティング", 電子情報通信学会技術研究報告 NS2022-58, Vol.122, No.105, pp.151-156, Jul 2022.
  13. 星野 優斗, 川上 大輝, 松谷 宏紀, "Neural ODEモデルを用いた連合学習の転送量削減", 電子情報通信学会技術研究報告 NS2022-59, Vol.122, No.105, pp.157-162, Jul 2022.
  14. 杉浦 圭祐, 松谷 宏紀, "深層学習を用いた経路計画手法のFPGAによる高速化", 電子情報通信学会技術研究報告 RECONF2022-1, Vol.122, No.60, pp.1-6, Jun 2022. (電子情報通信学会 リコンフィギャラブルシステム研究会 若手講演賞)
  15. 小島 瑠斗, 杉浦 圭祐, 松谷 宏紀, "FPGAを用いた点群データ向け特徴量ヒストグラムの並列処理", 電子情報通信学会技術研究報告 RECONF2022-23, Vol.122, No.60, pp.101-106, Jun 2022.
  16. 小島 瑠斗, 杉浦 圭祐, 松谷 宏紀, "3次元Lidar SLAMにおける精度劣化を考慮した点群データ量削減", 電子情報通信学会技術研究報告 CPSY2021-32, Vol.121, No.343, pp.78-83, Jan 2022. (電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞)
  17. 根本 研司, 古川 雅輝, 渡邉 寛悠, 松谷 宏紀, "オンライン逐次学習によるパケットルーティングの軽量機械学習手法", 電子情報通信学会技術研究報告 CPSY2021-35, Vol.121, No.343, pp.96-101, Jan 2022.
  18. 星野 優斗, 松谷 宏紀, "歩行ナビゲーションのための教師データ生成と連合学習の検討", 電子情報通信学会技術研究報告 NS2021-119, Vol.121, No.356, pp.50-55, Jan 2022.
  19. 伊藤 響, 松谷 宏紀, "単語分散表現のオンライン逐次学習を用いた更新方法", 電子情報通信学会技術研究報告 CPSY2021-17 (HotSPA'21), Vol.121, No.194, pp.31-36, Oct 2021.
  20. 古川 雅輝, 松谷 宏紀, "DPDKを用いた分散深層強化学習における経験サンプリングの高速化", 電子情報通信学会技術研究報告 CPSY2021-6 (SWoPP'21), Vol.121, No.116, pp.31-36, Jul 2021.
  21. 川上 大輝, 渡邉 寛悠, 杉浦 圭祐, 松谷 宏紀, "Neural ODEの軽量化モデルによる小規模FPGA向けドメイン適応", 電子情報通信学会技術研究報告 CPSY2021-10 (SWoPP'21), Vol.121, No.116, pp.53-58, Jul 2021.
  22. 杉浦 圭祐, 松谷 宏紀, "深層学習による2D点群レジストレーションのFPGA実装に関する一検討", 電子情報通信学会技術研究報告 RECONF2021-5, Vol.121, No.59, pp.20-25, Jun 2021.
  23. 川上 大輝, 渡邉 寛悠, 松谷 宏紀, "Neural ODEを用いたエッジデバイス向けドメイン適応手法", 電子情報通信学会技術研究報告 CPSY2020-67 (ETNET'21), Vol.120, No.435, pp.103-108, Mar 2021. (電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞)
  24. 山田 赳也, 塚田 峰登, 松谷 宏紀, "OS-ELMを用いたFPGA向け軽量ファインチューニング手法", 電子情報通信学会技術研究報告 CPSY2020-68 (ETNET'21), Vol.120, No.435, pp.109-114, Mar 2021.
  25. 渡邉 寛悠, 松谷 宏紀, "常微分方程式を用いたFPGAベースニューラルネットワークの評価", 電子情報通信学会技術研究報告 CPSY2020-30, Vol.120, No.338, pp.46-51, Jan 2021.
  26. 渡邉 寛悠, 松谷 宏紀, "常微分方程式を用いたニューラルネットワークのFPGA実装の検討", 電子情報通信学会技術研究報告 CPSY2020-21 (HotSPA'20), Vol.120, No.188, pp.22-27, Oct 2020.
  27. 塚田 峰登, 松谷 宏紀, "OS-ELMのための固定小数点ビット数の自動最適化", 電子情報通信学会技術研究報告 CPSY2020-4 (SWoPP'20), Vol.120, No.121, pp.23-28, Jul 2020.
  28. 杉浦 圭祐, 松谷 宏紀, "2次元グラフベースSLAMのFPGA実装に関する一検討", 電子情報通信学会技術研究報告 CPSY2020-8 (SWoPP'20), Vol.120, No.121, pp.49-54, Jul 2020.
  29. 岩田 拓真, 松谷 宏紀, "FPGA NICを用いた多次元多ストリーム変化点検出の高性能化", 電子情報通信学会技術研究報告 CPSY2019-94 (ETNET'20), Vol.119, No.428, pp.13-18, Feb 2020.
  30. 佐久間 拓哉, 松谷 宏紀, "オンライン逐次学習による時系列予測モデルを用いた人間の異常行動検出", 電子情報通信学会技術研究報告 CPSY2019-95 (ETNET'20), Vol.119, No.428, pp.35-40, Feb 2020.
  31. 四釜 快弥, 河野 隆太, Akram Ben Ahmed, 松谷 宏紀, 鯉渕 道紘, 天野 英晴, "バイパシングによる低遅延メモリパケットネットワーク", 電子情報通信学会技術研究報告 CPSY2019-93 (ETNET'20), Vol.119, No.428, pp.7-12, Feb 2020.
  32. 伊藤 怜, 塚田 峰登, 松谷 宏紀, "オンデバイス学習を用いた協調型モデル更新の高効率化", 電子情報通信学会技術研究報告 CPSY2019-65, Vol.119, No.372, pp.79-84, Jan 2020.
  33. 渡邉 寛悠, 塚田 峰登, 松谷 宏紀, "オンライン逐次学習アルゴリズムを用いた強化学習の軽量化", 電子情報通信学会技術研究報告 CPSY2019-66, Vol.119, No.372, pp.85-90, Jan 2020.
  34. 杉浦 圭祐, 松谷 宏紀, "2次元LiDAR SLAMアルゴリズムのFPGAによる高速化", 電子情報通信学会技術研究報告 CPSY2019-76, Vol.119, No.372, pp.151-156, Jan 2020. (情報処理学会 システム・アーキテクチャ研究会 若手奨励賞)
  35. 古川 雅輝, 井坪 知也, 松谷 宏紀, "ソフトウェアスイッチによるマルチGPU深層学習のパラメータ集約", 電子情報通信学会技術研究報告 CPSY2019-81, Vol.119, No.372, pp.175-180, Jan 2020. (電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞)

解説記事
  1. 松谷 宏紀, "エッジAIと実世界異常検知", OplusE, Vol.488, pp.608-613, Nov/Dec 2022.
  2. 松谷 宏紀, "ビッグデータ利活用のための基盤システムの動向", 電子情報通信学会誌, Vol.100, No.8, pp.866-870, Aug 2017. [Paper]

招待講演・チュートリアル講演
  1. 松谷 宏紀, "無線センサノード向けオンデバイス学習技術", 第53回エネルギーハーベスティングコンソーシアム (EHC) 総会, 招待講演, Jun 2023.
  2. 松谷 宏紀, "エッジ向けオンデバイス学習と連合学習", 電子情報通信学会技術研究報告 SR2023-22, Vol.123, No.19, p.93, 招待講演, May 2023.
  3. 松谷 宏紀, "組込みAIにおけるオンデバイス学習技術とその社会実装", STM32 Innovation Day 2022, 基調講演, Dec 2022.
  4. 松谷 宏紀, "置かれた環境で学習する無線センサ型異常検知システム", JSTイノベーション・ジャパン2022, セミナー講演, Oct 2022. [Slide]
  5. Hiroki Matsutani, "Neural Network ODL for Wireless Sensor Nodes", tinyML On Device Learning Forum, Aug 2022. [Slide] [Youtube Video]
  6. 松谷 宏紀, "TinyMLのための要素技術： 軽量モデル、オンデバイス学習、連合学習、アクセラレータ", CadenceLIVE Japan 2022, 招待講演, Jul 2022.
  7. 松谷 宏紀, "Beyond 5Gを見据えたIoT＋AI計算基盤", Pre-Keio Techno-Mall 2021セミナーシリーズ第1回, Sep 2021. [Slide]
  8. 松谷 宏紀, "エッジデバイスのためのオンデバイス学習技術", 電子情報通信学会技術研究報告 IBISML2020-41, Vol.120, No.395, p.33, 招待講演, Mar 2021.
  9. 松谷 宏紀, "オンデバイス学習とそのチップ化に向けて", 第18回AIチップ設計拠点フォーラム, 招待講演, Dec 2020.
  10. Hiroki Matsutani, "On-Device Learning and Its Applications: Toward Learning AI Chips", The 9th IEEE CPMT Symposium Japan (ICSJ'19), Special talk, Nov 2019.
  11. Hiroki Matsutani, "An On-Device Learning Approach for Unsupervised Anomaly Detection on Chip", The 13th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'19), Keynote talk, Oct 2019.
  12. 松谷 宏紀, "オンデバイス学習：教師データ無しで置くだけ異常検知", JST戦略的創造研究推進事業 新技術説明会, Sep 2019. [Slide] [Youtube Video]
  13. 松谷 宏紀, "オンデバイス学習とその応用～学習するAIチップ の実現に向けて～", 日本学術振興会 半導体界面制御技術第154委員会 第113回研究会, 招待講演, Sep 2019.
  14. 松谷 宏紀, "「オンデバイス学習」FPGA＋高位合成で推論だけ でなく学習も実行可能", FPGAでエッジAI技術セミナー, 日本電気株式会社, 基調講演, Jul 2019.
  15. Hiroki Matsutani, "An On-Device Learning Approach for Unsupervised Anomaly Detection", The 19th International Forum on MPSoC for Software-defined Hardware (MPSoC'19), Invited talk, Jul 2019. [Slide]
  16. 松谷 宏紀, "オンデバイス学習による教師無し異常検知ハード ウェアとその応用", LSIとシステムのワークショップ, 招待講演, May 2019.
  17. 松谷 宏紀, "オンライン逐次学習による教師無し異常検知とその応用", 情報処理学会研究報告 2018-ARC-233, 招待講演, Dec 2018.
  18. Hiroki Matsutani, "An Environmentally Adaptive Anomaly Detection Method for Edge Devices", The 6th International Symposium on Computing and Networking (CANDAR'18) Workshop, Invited talk, Nov 2018.
  19. 松谷 宏紀, "エッジ学習による環境適応型異常検知と実社会への応用", Design Solution Forum 2018, Sep 2018.
  20. Hiroki Matsutani, "Accelerating Anomaly Detection Algorithms on FPGA-Based High-Speed NICs", The 18th International Forum on MPSoC for Software-defined Hardware (MPSoC'18), Invited talk, Aug 2018. [Slide]
  21. Hiroki Matsutani, "A Building Block 3D System with Inductive-Coupling Through Chip Interfaces", The 36th IEEE VLSI Test Symposium (VTS'18), Special Session, Apr 2018. [Slide]
  22. Hiroki Matsutani, "Accelerator Design for Big Data Processing Frameworks", The 17th International Forum on MPSoC for Software-defined Hardware (MPSoC'17), Invited talk, Jul 2017. [Slide]
  23. 松谷 宏紀, "大量データを素早く処理: 最重要な難題を両立す るビッグデータAI処理基盤", JST研究開発戦略センター, ミニセミナー講演, Jun 2017.
  24. 松谷 宏紀, "ビックデータ利活用のための計算基盤", 電子情報通信学会技術研究報告 ICD2016-56, Vol.116, No.364, pp.29-32, 招待講演, Dec 2016. [Paper] [Slide]
  25. 鯉渕 道紘, 松谷 宏紀, 藤原 一毅, "大規模コンピュータ・ネッ トワークの建築学", 国立情報学研究所 H28年度第2回 産官学連携塾, Oct 2016. [My Slide]
  26. Hiroki Matsutani, "Accelerator Design for Various NOSQL Databases", The 16th International Forum on MPSoC for Software-defined Hardware (MPSoC'16), Invited talk, Jul 2016. [Slide]
  27. Hiroki Matsutani, "Inductive-Coupling 3D Wireless NoC Designs", The 29th International Conference on VLSI Design (VLSID'16), Special Session (Video Presentation), Jan 2016.
  28. 松谷 宏紀, "多様な構造型ストレージ技術を統合可能な再構成 可能データベース技術", 情報処理学会第77回全国大会, CREST・さきがけ「ビッグデータ」2領域 成果報告会, Mar 2015. [Niconico Video]
  29. Hiroki Matsutani, "Accelerator Design for Various NOSQL Databases", Big Data French-Japanese Workshop, The Embassy of France in Japan, Invited talk, Nov 2014.
  30. 松谷 宏紀, "ビッグデータ向け計算機アーキテクチャの研究動向と研究事例", インターネットコンファレンス2014 (IC'14), 招待講演, Nov 2014.
  31. 松谷 宏紀, "Open Cell Libraryを用いたデジタルVLSI設計", 電子情報通信学会2014年ソサイエティ大会, チュートリアル, Sep 2014. [Paper]
  32. Hiroki Matsutani, "3D WiNoC Architectures", The 8th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'14), Special Session, Sep 2014. [Slide]
  33. 松谷 宏紀, "ポリグロット永続化のためのNoSQLアクセラレータ", 情報処理学会研究報告 2014-DBS-159, 招待講演, Aug 2014.
  34. 松谷 宏紀, 川島 英之, "ビッグデータ研究最前線：最新研究事例の紹介から楽しい研究の始め方まで", 並列／分散／協調処理に関するサマーワークショップ (SWoPP'14), Birds-of-a-Feather, Jul 2014.
  35. 松谷 宏紀, "多様な構造型ストレージ（NOSQL）のためのアクセラレータ設計", 日本電気株式会社, 招待講演, Jul 2014.
  36. Hiroki Matsutani, "3D WiNoC Architectures", The 17th Design, Automation, and Test in Europe Conference (DATE'14), Tutorial, Mar 2014. [Slide]
  37. 松谷 宏紀, "ハードウェアによる様々な構造型ストレージの高速化", 情報処理学会第76回全国大会, パネル討論, Mar 2014. [Slide]
  38. Hiroki Matsutani, "Research Challenges on 2-D and 3-D Network-on-Chips", The 1st International Symposium on Computing and Networking (CANDAR'13), Tutorial, Dec 2013.
  39. 松谷 宏紀, "組込みシステム向けデータベース技術のハードウェア化に関する検討", 情報処理学会研究報告 2013-EMB-30, 招待講演, Sep 2013.
  40. Hiroki Matsutani, "A Wireless 3-D Network-on-Chip Architecture using Inductive-Coupling for Chip-Multiprocessors", Carnegie Mellon University, CSSI Seminar, Mar 2011.
  41. 松谷 宏紀, "Network-on-Chipの要素技術と最近の研究動向", 富士通株式会社, 招待講演, May 2010.
  42. 松谷 宏紀, "IEEE Computer Society Japan Chapter Young Author Award 2009 受賞記念講演", IEEE Computer Society Japan Chapter, Dec 2009.
  43. 井上 弘士, 木村 啓二, 松谷 宏紀, "メニーコア・プロセッサとそれを支える要素技術", 組込みシステムシンポジウム (ESS'09), チュートリアル, Oct 2009. [Slide]
  44. 松谷 宏紀, "Network-on-Chipアーキテクチャ最前線: 研究の始め方から最新動向まで", 福岡システムLSI総合開発センター, 招待講演, Aug 2008. [Slide]

Book Chapter
  1. Hiroki Matsutani, Keisuke Sugiura, "Chapter 17: Efficient Neural Networks and Their Acceleration Techniques for Embedded Machine Learning", Book of "Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Software Optimizations and Hardware/Software Codesign" edited by Sudeep Pasricha, Muhammad Shafique, pp.429-452, Springer, Oct 2023.
  2. Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "Chapter 10: 3-D NoC on Inductive Wireless Interconnect", Book of "3D Integration for NoC-based SoC Architectures" edited by Abbas Sheibanyrad, Frederic Petrot, Axel Janstch, pp.225-248, Springer, Dec 2010.
  3. Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, "Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks", Book of "Low Power Networks-on-Chip" edited by Cristina Silvano, Marcello Lajolo, Gianluca Palermo, pp.21-44, Springer, Oct 2010.
  4. Michihiro Koibuchi, Hiroki Matsutani, "Chapter 3: Networks-on-Chip Protocols", Book of "Networks-on-Chips: Theory and Practice" edited by Fayez Gebali, Haytham Elmiligi, Mohamed Watheq El-Kharashi, pp.65-94, CRC Press, Mar 2009.

受賞
  1. "IEEE TC Award for Editorial Service and Excellence" (2021).
  2. "Best Paper Award", The 8th International Symposium on Computing and Networking (CANDAR'20).
  3. "Best Paper Award", The 8th International Workshop on Computer Systems and Architectures (CSA'20).
  4. "情報処理学会 マイクロソフト情報学研究賞" (2018).
  5. "ACM Recognition of Service Award" (2018).
  6. "電子情報通信学会 情報・システムソサイエティ 査読功労賞" (2017).
  7. "Best Paper Award", The 4th International Symposium on Computing and Networking (CANDAR'16).
  8. "情報処理学会 特選論文" (2016).
  9. "Best Paper Award", The 6th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART'15).
  10. "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2014).
  11. "情報処理学会 計算機アーキテクチャ研究会 若手奨励賞" (2013).
  12. "Best Paper Award", The 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13).
  13. "Best Paper Award", The 2nd International Conference on Networking and Computing (ICNC'11).
  14. "船井情報科学振興財団 船井研究奨励賞" (2010).
  15. "IEEE Computer Society Japan Chapter Young Author Award" (2009).
  16. "電子情報通信学会 集積回路研究会 優秀若手講演賞" (2009).
  17. "情報処理学会 論文賞" (2008).
  18. "情報処理学会 山下記念研究賞" (2007).
  19. "IEEE Computer Society Japan Chapter Award", 先進的計算基盤システムシンポジウム (SACSIS'07).
  20. "Young Student Award", Student Forum at the 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07).
  21. "優秀論文賞", マルチメディア，分散，協調とモバイルシンポジウム (DICOMO'03).
  22. "デモンストレーション賞", インターネットコンファレンス (IC'02).

ノミネート

  1. "Best Paper Nominee", The 28th Reconfigurable Architectures Workshop (RAW'21).
  2. "Best Paper Candidate", The 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS'18).
  3. "Best Paper Candidate", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC'12).

共著者の受賞

  1. 杉浦 圭祐, "情報処理学会 コンピュータサイエンス領域奨励賞" (2023).
  2. 八幡 悠二郎, "電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞" (2023).
  3. 柴原 尚紀, "情報処理学会 システム・アーキテクチャ研究会 若手奨励賞" (2023).
  4. 塚田 峰登, "情報処理学会 システム・アーキテクチャ研究会 若手奨励賞" (2022).
  5. 杉浦 圭祐, "電子情報通信学会 リコンフィギャラブルシステム研究会 若手講演賞" (2022).
  6. 小島 瑠斗, "電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞" (2022).
  7. Keisuke Sugiura, "Poster Award", The 24th IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24).
  8. 川上 大輝, "電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞" (2021).
  9. 古川 雅輝, "電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞" (2020).
  10. 杉浦 圭祐, "情報処理学会 システム・アーキテクチャ研究会 若手奨励賞" (2020).
  11. 井坪 知也, "電子情報通信学会 コンピュータシステム研究会 優秀若手発表賞" (2019).
  12. Ryuta Kawano, "Outstanding Paper Award", The 6th International Symposium on Computing and Networking (CANDAR'18).
  13. 榊原 優真, "情報処理学会 コンピュータサイエンス領域奨励賞" (2018).
  14. 塚田 峰登, "情報処理学会 システム・アーキテクチャ研究会 若手奨励賞" (2018).
  15. 榊原 優真, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2018).
  16. 塚田 峰登, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2018).
  17. 徳差 雄太, "電気通信普及財団 テレコムシステム技術学生賞" (2018).
  18. Yao Hu, "Best Oral Presentation", The 1st International Conference on Cloud and Big Data Computing (ICCBDC'17).
  19. 林 愛美, "慶應義塾大学理工学研究科 藤原賞" (2017).
  20. 安戸 僚汰, "電気通信普及財団 テレコムシステム技術学生賞" (2017).
  21. 徳差 雄太, "学生奨励論文賞", インターネットコンファレンス (IC'16).
  22. 安戸 僚汰, "情報処理学会 山下記念研究賞" (2016).
  23. 尾崎 友哉, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2016).
  24. 河野 隆太, "電子情報通信学会 集積回路研究会 優秀若手講演賞" (2016).
  25. 林 愛美, "情報処理学会 システム・アーキテクチャ研究会 若手奨励賞" (2015).
  26. 徳差 雄太, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2015).
  27. 中原 浩, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2015).
  28. 森島 信, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2014).
  29. 加賀美 崇紘, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2014).
  30. Seiichi Tade, "Featured Poster Award", The 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII).
  31. 河野 隆太, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2013).
  32. Yusuke Koizumi, "Best Poster Award", The 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI).
  33. 川瀬 大樹, "情報処理学会 システムLSI設計技術研究会 優秀発表学生賞" (2012).
  34. 川口 雄輝, "情報処理学会 システムLSI設計技術研究会 優秀発表学生賞" (2012).
  35. 笹川 雄二郎, "電子情報通信学会 コンピュータシステム研究会 優秀若手講演賞" (2012).
  36. 小島 悠, "優秀若手研究賞", 先進的計算基盤システムシンポジウム (SACSIS'10).

学会活動

Journals

  1. IEEE Design & Test, Associate editor (Feb 2022 -).
  2. IEEE Transactions on Computers, Associate editor (Dec 2019 -).
  3. 電子情報通信学会和文論文誌 (通信ソサイエティ), 編集委員 (Jun 2023 -).
  4. IEICE Transactions on Information and Systems, Associate editor (May 2012 - Jun 2016).
  5. 情報処理学会論文誌 (JIP), 編集委員 (Jun 2012 - May 2016).
  6. IEICE Electronics Express (ELEX), Associate editor (May 2012 - Jun 2015).
  7. 情報処理学会論文誌, 組込みシステム工学特集, ゲスト副編集委員長 (Aug 2014, Feb 2015), ゲスト編集委員 (Dec 2012, Jul 2013, Feb 2014, Aug 2015, Feb 2016, Aug 2016, Feb 2017, Aug 2017, Feb 2018, Aug 2018, Feb 2019, Aug 2019, Feb 2020, Aug 2020, Mar 2021, Feb 2022, Sep 2022, Feb 2023).
  8. IEICE Transactions on Information and Systems, Special Section on Reconfigurable Systems, Guest editor (Feb 2018).
  9. IEICE Transactions on Information and Systems, Special Section on Parallel and Distributed Computing and Networking, Guest editor (Dec 2014), Guest associate editor (Dec 2015, Dec 2016, Dec 2017).
  10. 情報処理学会論文誌, 学生・若手研究者論文特集, ゲスト編集委員 (Mar 2015).
  11. IPSJ Transactions on System LSI Design Methodology (T-SLDM), Special Issue on ASP-DAC 2013, Guest associate editor (Aug 2013).
  12. IEICE Transactions on Electronics, Special Section on Hardware and Software Technologies on Advanced Microprocessors, Guest associate editor (Oct 2009).

Conferences

  1. International Forum on MPSoC for Software-defined Hardware (MPSoC), Organizing committee (Publicity chair 2016, Local organization chair 2019, Web chair 2024).
  2. Workshop on Parallel AI and Systems for the Edge (PAISE), Program committee (2024).
  3. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), Organizing committee (Secretary 2018, 2019, 2020, 2021, 2022, 2023, 2024).
  4. International Parallel and Distributed Processing Symposium (IPDPS), Program committee (2020, 2022, 2023).
  5. International Conference on Field Programmable Technology (ICFPT), Program committee (2023).
  6. International Symposium on Networks-on-Chip (NOCS), Organizing committee (Technical program chair 2016, General chair 2017), Program committee (2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023).
  7. International Conference on High Performance Computing, Data and Analytics (HiPC), Program committee (2022).
  8. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Program committee (2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022).
  9. The Cross-Disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG), プログラム委員 (2017, 2018, 2019, 2021, 2022).
  10. Design Automation Conference (DAC), Technical program committee (2017, 2018, 2020, 2021).
  11. International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), Program committee (2021).
  12. International Conference on High Performance Computing in Asia-Pacific Region (HPC-Asia), Program committee (2018, 2021).
  13. FPGA for HPC Workshop, Program committee (2021).
  14. International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures (ADMS), Program committee (2020).
  15. International Conference on Parallel Processing (ICPP), Technical program committee (2019).
  16. 組込みシステムシンポジウム (ESS), 組織委員 (プログラム副委員長 2016, プログラム副委員長 2017, プログラム副委員長 2018), プログラム委員 (2009, 2010, 2011, 2012, 2013, 2014, 2015, 2019).
  17. International Symposium on Microarchitecture (MICRO), ACM Student Research Competition (SRC) Selection committee (2018).
  18. International Symposium on Low Power Electronics and Design (ISLPED), Organizing committee (Design contest chair 2015), Technical program committee (2014, 2015, 2016, 2017, 2018).
  19. Design, Automation, and Test in Europe Conference (DATE), Technical program committee (2012, 2013, 2014, 2015, 2016, 2017).
  20. International Workshop on Data Management on New Hardware (DaMoN), Program Committee (2016, 2017).
  21. International Symposium on Computing and Networking (CANDAR), Program committee (2016, 2017).
  22. Annual Meeting on Advanced Computing System and Infrastructure (ACSI), Program committee (2015, 2016).
  23. International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS), Technical program committee (2016).
  24. Webとデータベースに関するフォーラム（WebDB Forum）, 実行委員会 (ローカルアレンジメント幹事 2016).
  25. Internet Conference, Technical program committee (2016).
  26. 情報処理学会 全国大会, 実行委員会 (委員 2016).
  27. International Green and Sustainable Computing Conference (IGSC), Technical program committee (2015).
  28. International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC), Technical program committee (2012, 2013, 2014, 2015).
  29. International Workshop on Many-core Embedded Systems (MES), Technical program committee (2014, 2015).
  30. Asia and South Pacific Design Automation Conference (ASP-DAC), Technical program committee (2012, 2013, 2014).
  31. International Conference on Reconfigurable Computing and FPGAs (ReConFig), Program committee (2013).
  32. International Conference on Parallel and Distributed Systems (ICPADS), Program committee (2013).
  33. International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Program committee (2013).
  34. International Symposium on Embedded Multicore Systems-on-Chip (MCSoC), Organizing committee (Publicity chair 2013), Program committee (2009, 2010, 2012, 2013).
  35. 先進的計算基盤システムシンポジウム (SACSIS), プログラム委員 (2012, 2013).
  36. International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA), Organizing committee (2011, 2012).
  37. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Technical program committee (2009, 2010, 2012).

SIGs

  1. 電子情報通信学会コンピュータシステム研究専門委員会 (SIG-CPSY), 専門委員 (Jun 2021 - present).
  2. 電子情報通信学会ネットワークシステム研究専門委員会 (SIG-NS), 専門委員 (Jun 2021 - present).
  3. 電子情報通信学会リコンフィギャラブルシステム研究専門委員会 (SIG-RECONF), 専門委員 (Jun 2014 - Jun 2020).
  4. 情報処理学会 データベースシステム研究会 (SIG-DBS), 運営委員 (Apr 2016 - Mar 2020).
  5. 情報処理学会 システムLSI設計技術研究会 (SIG-SLDM), 運営委員 (Apr 2011 - Mar 2015).
  6. 情報処理学会 組込みシステム研究会 (SIG-EMB), 運営委員 (Apr 2009 - Mar 2013).

講義
  1. 計算機基礎 (春学期), 慶應義塾大学理工学部, 2011, 2014 - 2022.
  2. アルゴリズム第2 (春学期), 慶應義塾大学理工学部, 2012 - 2022.
  3. 情報工学実験第2マイクロプロセッサ (秋学期), 慶應義塾大学理工学部, 2011 - 2022.
  4. VLSI設計演習 (春学期), 慶應義塾大学理工学部, 2011 - 2022.
  5. 分散システム特論 (秋学期), 慶應義塾大学理工学研究科, 2012 - 2022.

過去の講義

  1. プログラミング第3同演習 (秋学期), 慶應義塾大学理工学部, 2013.
  2. 情報処理 (夏期講習), 慶應義塾大学通信教育過程, 2011, 2012.