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Welcome to Matsutani Lab @ Keio University, Yokohama, Japan



Research

Our research topics broadly cover computing infrastructures of various types and scales ranging from edge to cloud computing. Currently, we are working on on-device AI (Artificial Intelligence) algorithms and their implementations for resource-limited edge devices, in-network computing using network-attached FPGAs and GPUs, and highly-efficient accelerators for machine learning and big data processing. Below are some selected research topics.

A publication list is here and summary of selected papers is here.

On-device learning for unsupervised anomaly detection (2017-present)

Toward on-device learning, we are working on a neural-network based online sequential learning and unsupervised anomaly detection (OSL-UAD) algorithm and its related technologies. In real environments, one of the biggest issues when applying AI is to prepare training data sets for all the possible situations, because noise pattern (e.g., vibration) fluctuates and status of products/tools varies with time. Our OSL-UAD learns normal patterns including noises in a placed environment extemporarily to detect unusual ones, so no prior training is needed. Below is a demo video.

You can find an overview of our research on “on-device learning for unsupervised anomaly detection” in the following invited talk slides and paper.

  • Hiroki Matsutani, “An On-Device Learning Approach for Unsupervised Anomaly Detection”, The 19th International Forum on MPSoC for Software-defined Hardware (MPSoC’19), Invited Talk, Jul 2019. [Slide]
  • Mineto Tsukada, et al., “A Neural Network Based On-device Learning Anomaly Detector for Edge Devices”, IEEE Transactions on Computers (TC), Jul 2020. (Featured Paper in July 2020) [Open Access]
  • Rei Ito, et al., “An On-Device Federated Learning Approach for Cooperative Anomaly Detection”, arXiv:2002.12301 (2020). [Paper]

In addition, we are working on ordinary differential equation (ODE) based neural networks for low-cost FPGA devices.

Acceleration of SLAM algorithms using FPGAs (2019-present)

For mobile robots, such as robot cleaners, UAVs, and wheel chairs, we are working on highly-efficient SLAM (Simultaneous Localization and Mapping) accelerators using small-sized FPGAs and optimization techniques for them.

In the following paper, a 2D LiDAR SLAM algorithm based on Rao-Blackwellized Particle Filter (RBPF) is accelerated by PYNQ-Z2 FPGA board.

  • Keisuke Sugiura, et al., “An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm”, arXiv:2006.01050 (2020). [Paper]

Acceleration of machine learning algorithms (2014-present)

For anomaly detection on high-bandwidth network traffic, we are working on anomaly detection algorithms on FPGA-based high-speed network interface card (network-attached FPGAs) including outlier detection (k-nearest neighbor, local outlier factor), change-point detection (SDAR), and anomaly behavior detection (HMM).
Below is a demo video in which ChangeFinder algorithm is implemented on a 10Gbps network-attached FPGA.

You can find an overview of our research on “acceleration on machine learning by network-attached FPGAs” in the following invited talk slides.

  • Hiroki Matsutani, “Accelerating Anomaly Detection Algorithms on FPGA-Based High-Speed NICs”, The 18th International Forum on MPSoC for Software-defined Hardware (MPSoC’18), Invited Talk, Aug 2018. [Slide]

Acceleration of various NoSQL data stores (2013-2019)

We are working on performance acceleration of various structured storages (aka NoSQLs) including key-value store, column-oriented store, document-oriented store, and graph database by using network-attached FPGAs and network-attached GPUs. We are also working on acceleration of bitcoin/blockchain search.
Below is a demo video in which a key-value store is accelerated by FPGA-based 10Gbit Ethernet network interface card.

You can find an overview of our research on “acceleration on various NoSQL data stores” in the following invited talk slides.

  • Hiroki Matsutani, “Accelerator Design for Various NOSQL Databases”, The 16th International Forum on MPSoC for Software-defined Hardware (MPSoC’16), Invited Talk, Jul 2016. [Slide]

Acceleration of big data processing frameworks (2014-present)

Big data processing system typically consists of various software components, such as message queuing, RPC, stream processing, batch processing, machine learning framework, and data stores. We are working on their performance acceleration by using network-attached FPGAs and network-attached GPUs.
Below is a demo video where Apache Spark is accelerated by network-attached GPUs via 10Gbit Ethernet. RDDs are cached in device memory of these remote GPUs.

In addition, stream processing is accelerated by a network-attached FPGA.
You can find an overview of our research on “acceleration on big data processing frameworks” in the following invited talk slides.

  • Hiroki Matsutani, “Accelerator Design for Big Data Processing Frameworks”, The 17th International Forum on MPSoC for Software-defined Hardware (MPSoC’17), Invited Talk, Jul 2017. [Slide]

Rack scale architecture for virtual reality (2015-2018)

As an example of our rack-scale architecture technology, remote GPUs connected via 10Gbit Ethernet are pooled and used for virtual reality applications on demand. Below is a demo video.

Data center network with light beam (2012-2018)

In the following demo video, a 40Gbps light beam is established between two computers and then virtual machine (VM) migration is performed using this “VM highway”.

3D stacking many-core processors with wireless chip interconnect (2009-2019)

You can find an overview of our research on “3D stacking many-core processors with wireless chip interconnect” in the following special session slides.

  • Hiroki Matsutani, “A Building Block 3D System with Inductive-Coupling Through Chip Interfaces”, The 36th IEEE VLSI Test Symposium (VTS’18), Special Session, Apr 2018. [Slide]

An NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers, called nocgen, is available at GitHub.



Address

Department of Information and Computer Science
3-14-1 Hiyoshi, Kouhoku-ku, Yokohama, Kanagawa, JAPAN 223-8522

Laboratory

Rooms: 26-207 and 26-210A
Yagami Campus, Keio University

Access

Yagami Campus Guide




Members

Associate Professor

Ph.D. Course Student

2nd-Year Master Course Students

  • Yuto Ozeki
  • Takuya Sakuma
  • Keisuke Sugiura
  • Masaki Furukawa
  • Hirohisa Watanabe

1st-Year Master Course Students

  • Hibiki Ito
  • Hiroki Kawakami
  • Takeya Yamada

4th-Year Bachelor Course Students

  • Yu Ikeda
  • Ryuto Kojima
  • Kenji Nemoto
  • Yuto Hoshino
  • Yujiro Yahata